Xilinx, Inc.

Tzu-No Chen

Hong Shi

Li-Sheng Weng

Po-Wei Chiu

Young Soo Lee

Disclosed herein is a chip package and method for fabricating the same are provided that includes a redistribution layer (RDL) with a plurality of loop and void structures. The chip package includes an integrated circuit (IC) die, and a package substrate. The RDL is disposed between the IC die and the package substrate. The RDL has RDL circuitry that connects the IC die to the package substrate. The RDL circuitry includes a first coil formed in a first metal layer and a second coil formed in a second metal layer. A first end of the second coil is coupled to a second end of the first coil by a first via. A second end of the second coil is the IC die.

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Kaohsiung, Taiwan

Tzu-No Chen