Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Nanjing Company, Limited

Tzu-Li Lee

Jian-Hong Lin

Yu-Ching Lee

Hsin-Chun Chang

Kuo-Yen Liu

Yih-Ching Wang

Hsien-Wei Chen

Keng-Chu Lin

Chih-Hao Chen

Ming-Chung Liang

Chia-Cheng Chou

Kang-Cheng Lin

Yen-Ming Chen

Pinyen Lin

Shang-Chieh Chien

Anthony Yen

Jeng-Horng Chen

Li-Te S Lin

Dian-Hau Chen

Chia-Hao Hsu

Chia-Chen Chen

Chih-Fan Huang

Tzer-Min Shen

Han-Yu Lin

Fang-Wei Lee

Tsiao-Chen Wu

Shu-Hao Chang

Tze-Chung Lin

Bi-Ling Lin

Mao-Nan Wang

Ying-Yu Chen

Chien Shih Tsai

Cheng-Tzu Yang

Raghunath Putikam

Chin Chuan Peng

Bor-Jou Wei

Kai-Tak Lam

Tzung-Luen Li

An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

Interconnect structure and forming method thereof

A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.

Semiconductor device and manufacturing method thereof

A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.

Method of fabricating semiconductor device including dummy via anchored to dummy metal layer

In some embodiments, the present disclosure relates to a method including forming an interconnect structure over a substrate. A bond pad may be coupled to the interconnect structure, and a polymeric material may be deposited over the bond pad. In some embodiments, the method further includes performing a patterning process to remove a portion of the polymeric material to form an opening in the polymeric material. The opening directly overlies and exposes the bond pad. Further, the method includes a first cleaning process. The polymeric material is cured to form a polymeric protection layer, and a second cleaning process is performed.

Method of forming a photoresist over a bond pad to mitigate bond pad corrosion

A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.

Semiconductor device including dummy via anchored to dummy metal layer

A method and apparatus for ultraviolet (UV) and extreme ultraviolet (EUV) lithography patterning is provided. A UV or EUV light beam is generated and directed to the surface of a substrate disposed on a stage and coated with photoresist. A laminar flow of a layer of inert gas is directed across and in close proximity to the substrate surface coated with photoresist during the exposure, i.e. lithography operation. The inert gas is exhausted quickly and includes a short resonance time at the exposure location. The inert gas flow prevents flue gasses and other contaminants produced by outgassing of the photoresist, to precipitate on and contaminate other features of the lithography apparatus.

Method and apparatus for ultraviolet (UV) patterning with reduced outgassing

A semiconductor structure for dissipating heat away from a resistor having neighboring devices and interconnects. The semiconductor structure includes a semiconductor substrate, a resistor disposed above the semiconductor substrate, and a thermal protection structure disposed above the resistor. The thermal protection structure has a plurality of heat dissipating elements, the heat dissipating elements having one end disposed in thermal conductive contact with the thermal protection structure and the other end in thermal conductive contact with the semiconductor substrate. The thermal protection structure receives the heat generated from the resistor and the heat dissipating elements dissipates the heat to the semiconductor substrate.

Method and structure for dissipating heat away from a resistor having neighboring devices and interconnects

A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Method for forming semiconductor structure having protection layer for preventing laser damage

A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.

Method for fabricating low-k dielectric and Cu interconnect

A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Protection layer for preventing laser damage on semiconductor devices

An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

Process for improving the reliability of interconnect structures and resulting structure

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Yunlin, Taiwan

Tzu-Li Lee