Taiwan Semiconductor Manufacturing Comp. Ltd.

Tzu-Hsiang Hsu

Feng-Cheng Yang

Wei-Yang Lee

Yen-Ru Lee

Ting-Yeh Chen

Hsueh-Chang Sung

Chien-Wei Lee

Chii-Horng Li

Chih-Yun Chin

Teng-Chun Tsai

Chia-Jung Hsu

Heng-Wen Ting

Yen-Ming Chen

Pei-Ren Jeng

Yan-Ting Lin

Roger Tai

Davie Liu

Gin-Chen Huang

Jyun-Chih Lin

Mei-Yun Wang

Fu-Kai Yang

Chen-Ming Lee

Ying-Ho Chen

Chun Po Chang

Hung Lo

Shih-Hao Lin

Hsin-Wen Su

Chih-Hsiang Huang

Szu-Chi Yang

Chong-De Lien

A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.

Semiconductor device and method

A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.

Method for epitaxial growth and device

An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.

Interfacial layer between fin and source/drain region

A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins with a first gate pitch and second gate structures engaging the second fins with a second gate pitch smaller than the first gate pitch. The semiconductor structure also includes first epitaxial semiconductor features partially embedded in the first fins and adjacent the first gate structures and second epitaxial semiconductor features partially embedded in the second fins and adjacent the second gate structures. A bottom surface of the first epitaxial semiconductor features is lower than a bottom surface of the second epitaxial semiconductor features.

Semiconductor structure with improved source drain epitaxy

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

Semiconductor device with tunable epitaxy structures and method of forming the same

A semiconductor device includes a layer having a semiconductive material. The layer includes an outwardly-protruding fin structure. An isolation structure is disposed over the layer but not over the fin structure. A first spacer and a second spacer are each disposed over the isolation structure and on sidewalls of the fin structure. The first spacer is disposed on a first sidewall of the fin structure. The second spacer is disposed on a second sidewall of the fin structure opposite the first sidewall. The second spacer is substantially taller than the first spacer. An epi-layer is grown on the fin structure. The epi-layer protrudes laterally. A lateral protrusion of the epi-layer is asymmetrical with respect to the first side and the second side.

FinFET having non-merging epitaxially grown source/drains

Interfacial layer between Fin and source/drain region

A semiconductor structure includes a semiconductor fin disposed over a substrate, a metal gate stack disposed over the semiconductor fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the metal gate stack, and a dielectric feature embedded in the semiconductor fin, where a bottom surface of the epitaxial S/D feature is disposed on a top surface of the dielectric feature, and where sidewalls of the epitaxial S/D feature extend to define sidewalls of the dielectric feature.

Methods of forming epitaxial source/drain features in semiconductor devices

A transistor is provided including a source-drain region, the source-drain region including a first layer wherein a first average silicon content is between about 80% and 100%, a second layer wherein a second average silicon content is between zero and about 90%, the second average silicon content being smaller than the first average silicon content by at least 7%, and the second layer disposed on and adjacent the first layer, a third layer wherein a third average silicon content is between about 80% and 100%, and a fourth layer wherein a fourth average silicon content is between zero and about 90%, the fourth average silicon content being smaller than the third average silicon content by at least 7%, and the fourth layer disposed on and adjacent the third layer.

Method of epitaxy and semiconductor device

A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region. Each of the plurality of buffer layers may have an average thickness in a range of about 2 &#x212b; to about 30 &#x212b;.

A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch that is smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins, second gate structures engaging the second fins, first epitaxial semiconductor features adjacent the first gate structures, and second epitaxial semiconductor features adjacent the second gate structures. The first epitaxial semiconductor features are partially embedded in the first fins at a first depth, and the second epitaxial semiconductor features are partially embedded in the second fins at a second depth that is smaller than the first depth.

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Xinfeng, China

Tzu-Hsiang Hsu