Taiwan Semiconductor Manufacturing Comp. Ltd.

Université De Technologie De Troyes

Phaselab Instrument

Tzu-Heng Wu

Chun-Ren Cheng

Chun-Wen Cheng

Yi-Hsien Chang

Chia-Hua Chu

Yi-Heng Tsai

Wei-Cheng Shen

Shih-Wei Lin

Jung-Kuo Tu

Yi Heng Tsai

Fu-Chun Huang

Han-Chin Chiu

Chii-Wann Lin

Chun-Yin Tsai

Li-Chen Yen

Wen-Cheng Kuo

Kai-Chih Liang

Chen Hsiung Yang

Cheng San Chou

Ming-Dao Wu

Aurélien Bruyant

Julien Vaillant

An integrated microphone device is provided. The integrated microphone device includes a substrate, a plate, and a membrane. The substrate includes an aperture allowing acoustic pressure to pass through. The plate is disposed on a side of the substrate. The membrane is disposed between the substrate and the plate and movable relative to the plate as acoustic pressure strikes the membrane. The membrane includes a vent valve having an open area that is variable in response to a change in acoustic pressure.

Integrated microphone device and manufacturing method thereof

A method includes forming a recess in a first substrate, bonding a micro-electro-mechanical systems (MEMS) substrate to the first substrate after forming the recess in the first substrate, forming an anti-stiction layer over the micro-electro-mechanical systems (MEMS) substrate, pattering the anti-stiction layer, etching the MEMS substrate to form a MEMS device, and bonding the MEMS device and the first substrate to a second substrate. The patterned anti-stiction layer is between the MEMS device and the second substrate.

Method of fabricating semiconductor structure

A substrate structure for a micro electro mechanical system (MEMS) device, a semiconductor structure and a method for fabricating the same are provided. In various embodiments, the substrate structure for the MEMS device includes a substrate, the MEMS device, and an anti-stiction layer. The MEMS device is over the substrate. The anti-stiction layer is on a surface of the MEMS device, and includes amorphous carbon, polytetrafluoroethene, hafnium oxide, tantalum oxide, zirconium oxide, or a combination thereof.

Substrate structure, semiconductor structure and method for fabricating the same

A semiconductor structure includes a first substrate, a second substrate disposed over the first substrate, and including a first surface, a second surface opposite to the first surface, a via portion extending between the first surface and the second surface, a first through hole and a second through hole, and a device disposed over the second surface, and including a dielectric layer, a backplate at least partially exposed from the dielectric layer and a membrane at least partially exposed from the dielectric layer and disposed between the backplate and the first substrate, wherein the via portion is disposed within the second through hole, and the dielectric layer is bonded with the second substrate, and the device is electrically connected to the first substrate through the via portion.

Semiconductor structure and manufacturing method thereof

A MEMS device includes a substrate, a supporter, a first back plate, a second back plate and a diaphragm. The substrate has a cavity. The supporter is over the substrate. The first back plate is over the cavity and fixed on the supporter. The second back plate is over the cavity and fixed on the supporter. The diaphragm is between the first back plate and the second back plate. The diaphragm includes a first sub-diaphragm and a second sub-diaphragm over the cavity and fixed on the supporter.

MEMS device and manufacturing method thereof

A method of manufacturing a semiconductor structure includes receiving a first substrate including a dielectric layer disposed over the first substrate; forming a sensing structure and a bonding structure over the dielectric layer; disposing a conductive layer on the sensing structure; disposing a barrier layer over the dielectric layer; removing a first portion of the barrier layer to at least partially expose the conductive layer on the sensing structure; and removing a second portion of the barrier layer to at least partially expose the bonding structure.

A semiconductor structure includes a substrate, a dielectric layer disposed over the substrate, a sensing structure disposed over the dielectric layer, a bonding structure disposed over the dielectric layer, a conductive layer covering the sensing structure, and a barrier layer disposed over the dielectric layer, the conductive layer and the bonding structure, wherein the conductive layer and the bonding structure are at least partially exposed from the barrier layer.

An integrated circuit (IC) structure is provided. The IC structure includes an IC substrate including active devices which are coupled together through a conductive interconnect structure arranged thereover. The conductive interconnect structure includes a series of horizontal conductive layers and dielectric regions arranged between neighboring horizontal conductive layers. The conductive interconnect structure includes an uppermost conductive horizontal region with a planar top surface region. A MEMS substrate is arranged over the IC substrate and includes a flexible or moveable structure that flexes or moves commensurate with a force applied to the flexible or moveable structure. The active devices of the IC substrate are arranged to establish analysis circuitry to facilitate electrical measurement of a capacitance between the uppermost conductive horizontal region and the flexible or moveable structure.

Capacitor with planarized bonding for CMOS-MEMS integration

A three-dimensional (3D) integrated circuit (IC) includes a first IC and a second IC. The first IC includes a MEMS device and a first bonding structure. The second IC includes a second bonding structure. The first and second bonding structures are bonded together to couple the first IC to the second IC. A conformal barrier layer is disposed over a surface of the second IC nearest the first IC. An etch isolation structure is arranged beneath the surface of the second IC and encloses a sacrificial region which is arranged on either side of the second bonding structure and which is arranged in the second IC.

Isolation structure for MEMS 3D IC integration

The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.

Growing community of inventors

Taipei, Taiwan

Tzu-Heng Wu