Taiwan Semiconductor Manufacturing Comp. Ltd.

Tzong-Sheng Chang

Bor-Zen Tien

Kuang-Hsin Chen

Tsung-Yu Chiang

Chrong-Jung Lin

Ya-Chin King

Chi-Hung Liao

Kuei-Shun Chen

Shih-Chi Fu

Fei-Gwo Tsai

Jui-Ping Chuang

Meng-Wei Chen

Hsueh-Yi Chung

Chen Kuang-Hsin

Chen-Cheng Chou

Mu-Yi Lin

Wei-Ti Hsu

Jhu-Ming Song

Hsuan-Han Lin

Yung-Cheng Chen

Huang-Kui Chen

Woan-Yun Hsiao

Min Cao

Yu-Hua Lee

Wei-Shuo Ho

Chen Cheng Chou

Chia-Hung Lai

Jiunn-Jyi Lin

Huan-Chi Tseng

Chin-Tien Yang

Jieh-Ting Chang

Wen-Jye Yue

Yung-Fu Shen

An-Lun Lo

Chih-Lin Wang

Song-Bor Lee

Hsun-Chih Tsao

Yen-Shih Ho

Jenn Tsao

Yi-Huang Wu

Cheng-Te Lin

Ruey-Hsin Liou

Yuan-Cheng Yu

Yung-cheng Chen

Shih-Chang Huang

Hung-Chi Tsai

Sheng-Ching Chen

A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.

Method of fabricating reticle

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure. In addition, the first conductive structure is in direct contact with the first source/drain structure, and the second conductive structure is not in direct contact with the second source/drain structure.

Semiconductor structure with data storage structure and method for manufacturing the same

An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.

Method for forming interconnect structure

A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.

Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.

Methods for manufacturing semiconductor arrangements using photoresist masks

Semiconductor structure with data storage structure

Back-end-of-line (BEOL) arrangement with multi-height interlayer dielectric (ILD) structures

Method of manufacturing a semiconductor structure including a plurality of trenches

Exposure method of wafer substrate, manufacturing method of semiconductor device, and exposure tool

Semiconductor arrangement having an overlay alignment mark with a height shorter than a neighboring gate structure

A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack, a second gate stack, and a third gate stack, which are positioned over a semiconductor substrate and spaced apart from each other. The method includes removing portions of the semiconductor substrate to form a first recess, a second recess, and a third recess in the semiconductor substrate. The method includes forming a first doped structure, a second doped structure, and an isolation structure in the first recess, the second recess, and the third recess respectively. The first gate stack, the second gate stack, the first doped structure, and the second doped structure together form a memory cell. The isolation structure is wider and thinner than the second doped structure. A top surface of the isolation structure has a fourth recess.

Method for forming semiconductor device structure

A method comprises forming a plurality of interconnect components over a gate structure, wherein a bottom metal line of the interconnect components is connected to the gate structure through a gate plug, depositing a dielectric layer over a top metal line of the interconnect components, forming an opening in the dielectric layer, depositing a first barrier layer on a bottom and sidewalls of the opening using a non-plasma based deposition process, depositing a second barrier layer over the first barrier layer using a plasma based deposition process and forming a pad in the opening.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack positioned over the semiconductor substrate. The semiconductor device structure includes a first doped structure and a second doped structure positioned at two opposite sides of the first gate stack and embedded in the semiconductor substrate. The semiconductor device structure includes a second gate stack positioned over the semiconductor substrate and adjacent to the second doped structure. The semiconductor device structure includes a third gate stack positioned over the semiconductor substrate. The semiconductor device structure includes an isolation structure embedded in the semiconductor substrate and between the second gate stack and the third gate stack. The isolation structure is wider and thinner than the second doped structure, and the isolation structure is made of an epitaxial material.

Semiconductor device structure and method for forming the same

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Chubei, Taiwan

Tzong-Sheng Chang