Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

TSMC Nanjing Company, Limited

Tzer-Min Shen

Zhiqiang Wu

Yen-Tien Tung

Pinyen Lin

Dhanyakumar Mahaveer Sathaiya

Jhih-Rong Huang

Chih-Hao Wang

Kuan-Lun Cheng

Cheng-Tung Huang

Tzyy-Ming Cheng

Ching-Wei Tsai

Chung-Liang Cheng

Keng-Chu Lin

Shyh-Fann Ting

Chung-Cheng Wu

Ken-Ichi Goto

Min Cao

Yi-Chung Sheng

Wen-Han Hung

Han-Yu Lin

Hsiang-Pi Chang

Carlos H Diaz

Li-Te S Lin

Sung-Li Wang

Wei-Hao Wu

Wen-Hsing Hsieh

Huang-Lin Chao

Mrunal Abhijith Khaderbad

Yi-Ming Sheu

Chia-Hung Chu

Tsung-Hsing Yu

Chung-Wei Wu

Hua Feng Chen

Chun-Fu Cheng

Hsu-Kai Chang

Kuan-Ting Liu

Chia-Wen Liu

Ya-Yun Cheng

Szu-Wei Huang

Yao-Sheng Huang

Yin-Chuan Chuang

Ting-Yun Wu

Zhi-Ren Xiao

Yung-Chien Huang

Hong-Shen Chen

Sai-Hooi Yeong

Shuen-Shin Liang

Fu-Ting Yen

Huan-Sheng Wei

Huang-Siang Lan

Sathaiya Mahaveer Dhanyakumar

Khaderbad Mrunal Abhijith

Mahaveer Sathaiya Dhanyakumar

Gary Chan

Dawei Heh

Yu-Ming Lin

Kuo-Cheng Ching

Chi On Chui

Chung-Te Lin

Bo-Feng Young

Weng Chang

Hsin-Yi Lee

Chun-Chieh Lu

Cheng-Ming Lin

Chansyun David Yang

Kun-Hsien Lee

Fang-Wei Lee

I-Ming Chang

Nien-Chung Li

Chia-Wen Liang

Chi-Hsing Hsu

Ying-Chih Chen

Li-Shian Jeng

Tze-Chung Lin

Wei-Yen Woon

Kun-Yu Lee

Chun-I Wu

Tzu-Li Lee

Blanka Magyari-Kope

Yu-Chia Liang

Szu-Hua Chen

Cheng-Tzu Yang

Jing-Chang Wu

Raghunath Putikam

I-ming Chang

Yu-Chuan Shih

Ching-Chang Wu

Kai-Tak Lam

Shen-Yang Lee

Qing Shi

A semiconductor device includes a substrate, an interfacial layer formed on the semiconductor substrate, and a high-k dielectric layer formed on the interfacial layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity. A first concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the p-type transistor is different from a second concentration ratio of the first concentration of the first dopant species to the second concentration of the second dopant species of the n-type transistor.

Dipoles in semiconductor devices

A semiconductor device includes a channel layer, an interfacial layer, a gate dielectric layer, a gate electrode, dipole elements, and additional elements. The interfacial layer is disposed on the channel layer, and includes an insulating material. The gate dielectric layer is disposed over the interfacial layer such that the channel layer is separated from the gate dielectric layer by the interfacial layer. The gate electrode is disposed on the gate dielectric layer. The dipole elements are present in at least one of the interfacial layer and the gate dielectric layer in a predetermined amount such that the semiconductor device has a predetermined threshold voltage. The additional elements are located at a region where the dipole elements are present so as to reduce interfacial defects caused by the dipole elements. The additional elements are different from the dipole elements. Methods for manufacturing the semiconductor device are also disclosed.

Semiconductor device with tunable threshold voltage and method for manufacturing the same

A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.

Effective work function tuning via silicide induced interface dipole modulation for metal gates

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

Integrated circuit structure and method with hybrid orientation for FinFET

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a (001) surface, the first nanostructure has a first channel direction on the (001) surface, and the first channel direction is [0 1 0] or [0 −1 0]. The semiconductor device structure includes a gate stack surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack. The first nanostructure is between the first source/drain structure and the second source/drain structure, and the first channel direction is from the first source/drain structure to the second source/drain structure.

Semiconductor device structure with channel and method for forming the same

A semiconductor device includes a first electrode layer, a ferroelectric layer, a first alignment layer and a second electrode layer. A material of the first alignment layer includes rare-earth metal oxide. The ferroelectric layer and the first alignment layer are disposed between the first electrode layer and the second electrode layer, and the first alignment layer is disposed between the ferroelectric layer and the first electrode layer.

Semiconductor devices including FTJ structure

The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

Spacer structure for semiconductor device and method for forming the same

Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

2D-channel transistor structure with source-drain engineering

A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Gate structure in semiconductor device and method of forming the same

The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Graphene layer for low resistance contacts and damascene interconnects

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.

Dual channel structure

A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Contact structures in semiconductor devices

A memory circuit includes a memory array including a plurality of memory cells, each memory cell of the plurality of memory cells including an n-type channel layer including a metal oxide material, and a gate structure overlying and adjacent to the n-type channel layer, the gate structure including a conductive layer overlying a ferroelectric layer. The memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations, the gate voltage has a positive polarity and a first magnitude in the first write operation and a negative polarity and a second magnitude greater than the first magnitude in the second write operation.

Memory circuit and write method

A semiconductor device includes a semiconductor substrate, an interfacial layer formed on the semiconductor substrate, a high-k dielectric layer formed on the interfacial layer, and a conductive gate electrode layer formed on the high-k dielectric layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity, and the first and second polarities are opposite.

Growing community of inventors

Hsinchu, Taiwan

Tzer-Min Shen