Kabushiki Kaisha Toshiba

Tutomu Tamaki

Kiyomi Naruke

A method for manufacturing a semiconductor device having N-type source and drain regions formed substantially in parallel to each other in the surface of a P-type semiconductor substrate. A channel region having first to fourth edges are sandwiched between each pair of the source and drain regions on the first and second edges. A gate insulating film is formed on the semiconductor substrate. Gate electrodes are formed substantially in parallel to each other on the semiconductor substrate via gate insulating film so as to cross the source and drain regions. The first and second edges of the channel regions are substantially parallel to the source and drain regions, and third and fourth regions are substantially parallel to the gate electrodes. A P-type impurity diffusion region is formed by ion implantation in accordance with self-alignment with gate electrodes, at least on either side of the third and fourth edge of at least one of the channel regions. An impurity concentration of the impurity diffusion region is adjusted such that it is higher than that of the semiconductor substrate.

Method for manufacturing a semiconductor device having an adjustable

A semiconductor device having N-type source and drain regions formed substantially in parallel to each other in the surface of a P-type semiconductor substrate. A channel region having first to fourth edges are sandwiched between each pair of the source and drain regions on the first and second edges. A gate insulating film is formed on the semiconductor substrate. Gate electrodes are formed substantially in parallel to each other on the semiconductor substrate via gate insulating film so as to cross the source and drain regions. The first and second edges of the channel regions are substantially parallel to the source and drain regions, and third and fourth regions are substantially parallel to the gate electrodes. A P-type impurity diffusion region is formed by ion implantation in accordance with self-alignment with gate electrode, at least on either of the third or fourth edge of at least one of the channel regions. An impurity concentration of the impurity diffusion region is adjusted such that it is higher than that of the semiconductor substrate.

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Yokohama, Japan

Tutomu Tamaki