Taiwan Semiconductor Manufacturing Comp. Ltd.

Tung-Heng Hsieh

Bao-Ru Young

Sheng-Hsiung Wang

Yung Feng Chang

Hui-Zhong Zhuang

Chung-Te Lin

Li-Chun Tien

Ting-Wei Chiang

Chun-Chia Hsu

Tzung-Chi Lee

Chia-Sheng Fan

Tsung-Chieh Tsai

Jyh-Kang Ting

Juing-Yi Wu

Liang-Yao Lee

Chun-Yen Lin

Yi-Jyun Huang

Hsien-Huang Liao

Ru-Gun Liu

Yu-Jung Chang

Pang-Chi Wu

Yung-Feng Chang

Mei-Yun Wang

Chung-Hui Chen

Kuo-Yi Chao

Min-Hsiung Chiang

Chin-Shan Hou

Shih-Chieh Wu

Chih-Hung Wang

Yimin Huang

Pai-Chieh Wang

Jam-Wem Lee

Kuo-Feng Yu

Jian-Hao Chen

Jiun-Ming Kuo

Shyue-Shyh Lin

Tsung-Lin Wu

Chia-Yu Lu

Yu-Cheng Yeh

Ming-Yang Huang

Tun-Jen Chang

Chun-Yi Lee

Yi-Fan Chen

Shao-Jyun Wu

Yu-Bey Wu

Chien-Li Cheng

Shu-Wei Chung

Che-Yuan Hsu

Tun Jen Chang

Pi-Yun Sun

Yuan-Te Hou

Yen-Hung Lin

Tsung-Hsin Yu

Sun-Jay Chang

Yi-Shien Mor

Hsien-Chin Lin

Chung-Yi Lin

Wan-Te Chen

Yung-Shun Chen

Wang-Jung Hsueh

Tzu-Ching Chang

Che-Yuan Che

Yung-Shen Chen

Hao Kuang

Provided is a tap cell including a substrate, a first well, a second well, a first doped region, and the second doped region. The substrate has a first region and a second region. The first well has a first dopant type and includes a first portion disposed in the first region and a second portion extending into the second region. The second well has a second dopant type and includes a third portion disposed in the second region and a fourth portion extending into the first region. The first doped region having the first dopant type is disposed in the second portion of the first well and the third portion of the second well along the second region. The second doped region having the second dopant type is disposed in the first portion of the first well and the fourth portion of the second well along the first region.

Integrated circuit structure having tap cell

An integrated circuit (IC) layout design is received that includes a first circuit cell and a second circuit cell abutted to one another. The first circuit cell contains a first IC component, and the second circuit cell contains a second IC component. A determination is made that a distance between the first IC component and the second IC component is less than a predefined threshold when the first circuit cell and the second circuit cell are abutted together. The IC layout design is revised such that the distance between the first IC component and the second IC component is eliminated in the revised IC layout design.

Revising IC layout design to eliminate gaps between isolation structures

The integrated circuit (IC) structure includes a semiconductor substrate, a first active region, a dummy fill region, a second active region, first metal gate structures, and second metal gate structures. The first active region is on the semiconductor substrate. The dummy fill region is on the semiconductor substrate. The second active region is on the semiconductor substrate and spaced apart from the first active region by the dummy fill region. The first metal gate structures extend in the first active region and have a first gate pitch and a first gate width. The second metal gate structures extend in the second active region and have a second gate width greater than the first gate width and a second gate pitch being an integer times the first gate pitch, and the integer being two or more.

Integrated circuit structure with gate structures on grids and method for forming the same

A method includes forming first and second semiconductor fins protruding from a substrate. Each of the first and second semiconductor fins includes a stack of alternating channel layers and non-channel layers. The method also includes forming a dielectric helmet between and protruding from the first and the second semiconductor fins, forming a dummy gate stack over the dielectric helmet, patterning the dummy gate stack to expose a portion of the dielectric helmet, removing the exposed portion of the dielectric helmet, and forming a metal gate structure, such that a remaining portion of the dielectric helmet separates the metal gate structure between the first and the second semiconductor fins. The method also includes forming a contact feature over a portion of the metal gate structure. A sidewall of the contact feature is between one of the semiconductor fins and the remaining portion of the dielectric helmet.

Gate isolation features in semiconductor devices and methods of fabricating the same

An integrated circuit includes a first gate electrode structure extending in a first direction. The integrated circuit includes a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The integrated circuit includes a conductive feature. The conductive feature includes a first section electrically connected to the second portion, a second section electrically connected to the second gate structure, and a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction.

Integrated circuit having angled conductive feature

A method for forming a pattern layout is provided, including receiving an IC design layout including a layout block, a first line pattern is disposed inside the layout block along the first direction; forming a second line pattern disposed outside the layout block parallel to the first line patterns; forming a mandrel bar pattern oriented along the second direction and overlapping the first line pattern and the second line pattern, the mandrel bar pattern is between the first edge and the third edge of the layout block that are parallel to the first direction, and a first end of the mandrel bar pattern is separated from the first edge and overlaps a first side edge of one of the first line pattern or the second line pattern closest to the first edge; and outputting a pattern layout.

Methods for forming pattern layout, mask, and semiconductor structure

In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

Semiconductor devices

A semiconductor structure includes a substrate; a first column of active regions over the substrate; a second column of active regions over the substrate; and a dummy padding disposed between the first and the second columns from a top view. The dummy padding includes multiple dummy regions. A first dummy region of the multiple dummy regions is disposed between a first active region in the first column of active regions and a second active region in the second column of active regions. An outer boundary line tracing an edge of the first active region, an edge of the first dummy region, and an edge of the second active region includes at least two substantially 90-degree bends from a top view. The first and the second active regions include a semiconductor material doped with a same dopant.

Standard cell design with dummy padding

A fuse structure includes first and second transistors where each of the first and the second transistors has a source terminal, a drain terminal, and a gate terminal; a first source/drain contact disposed on the source terminal of the first transistor; a second source/drain contact disposed on the drain terminal of the second transistor; an insulator disposed laterally between the first and the second source/drain contacts; a source/drain contact via disposed on the first source/drain contact; and a program line connected to the source/drain contact via, wherein a width of the insulator is configured such that a programming potential applied across the source/drain contact via and the drain terminal of the second transistor causes the insulator to break down.

Fuse structure

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The fin has a wide portion and a width-transition portion. The width-transition portion tapers away from the wide portion in a top view of the substrate, and a first top surface of the wide portion is higher than a second top surface of the width-transition portion. The semiconductor device structure includes a gate stack wrapped around the wide portion. The semiconductor device structure includes a dielectric dummy gate wrapped around the width-transition portion.

Semiconductor device structure with dielectric dummy gate and method for forming the same

A method for making an integrated circuit (IC) includes inserting black boxes into a layout of the IC; connecting the black boxes with a connectivity network; and inserting first dummy patterns in areas of the layout outside of the black boxes and the connectivity network. After the inserting of the first dummy patterns, the method further includes replacing the black boxes with circuit macros that have one-to-one correspondence with the black boxes, wherein each of the circuit macros includes circuit patterns in a central area of the respective circuit macro and second dummy patterns surrounding the central area. In the method, at least one of the following operations is performed by an electronic design automation (EDA) tool: the inserting of the black boxes, the connecting of the black boxes, the inserting of the first dummy patterns, and the replacing of the black boxes with the circuit macros.

Method for chip integration

A semiconductor device structure and a formation method are provided. The method includes forming a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure over a substrate. The second fin structure is between the first fin structure and the third fin structure, and the third fin structure is between the second fin structure and the fourth fin structure. A first lateral distance between the first and the second fin structures is greater than a second lateral distance between the third and the fourth fin structures. The method also includes forming a first p-type epitaxial structure over the first fin structure and forming a second p-type epitaxial structure over the second fin structure. The method further includes forming a first n-type epitaxial structure over the third fin structure and forming a second n-type epitaxial structure over the fourth fin structure.

Structure and formation method of semiconductor device with epitaxial structures

A method for forming a semiconductor device structure includes forming a fin structure with alternating stacked first semiconductor layers and second semiconductor layers over a substrate. The method also includes forming a cladding layer over the fin structure. The method also includes forming a fin isolation structure beside the cladding layer. The method also includes forming a capping layer over the fin isolation structure. The method also includes forming a dummy gate structure across the capping layer. The method also includes patterning the dummy gate structure. The method also includes patterning the capping layer by using the dummy gate structure as a mask layer. The method also includes removing the dummy gate structure.

Semiconductor device structure and method for forming the semiconductor device structure

A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.

Semiconductor devices having fins and multiple isolation regions

An IC includes a first standard cell (SC) having a first circuit area (CA) and a first transition area (TA) placed on an edge of the CA; and a SChaving a CAand a TAplaced on an edge of CA'. CAincludes a first and a second active region (ARand AR) longitudinally oriented along a first direction (D), and a first gate stack (G) along a D⊥Dand extending over ARand AR. Gincludes a first gate segment (GS) contacting ARand a GScontacting AR. GSand GSare different in composition. GSand GSare associated with a pFET and a nFET, respectively. TAincludes a Glongitudinally oriented along Dand spans between opposite cell edges of the SC. Gis a lengthwise uniform gate stack. SCis placed in abutment with the SCsuch that TAand TAshare a common edge.

Integrated standard cell structure

Growing community of inventors

Zhudong Town, Taiwan

Tung-Heng Hsieh