Mosel Vitelic Corporation

Tun-Fu Hung

Chih-Ta Wu

Shih-Chi Lai

Yi-Fu Chung

Yi Fu Chung

Jen Chieh Chang

Jen-Chieh Chang

Ming-Ren Chi

Wen-Jet Su

A fabrication method for forming a gate structure through an amorphous silicon layer includes providing a substrate layer, forming an amorphous silicon layer of a selected thickness on the substrate layer at a reaction temperature between about 520&#xb0; C. and 560&#xb0; C., and forming a doped amorphous silicon layer in a upper portion of the amorphous silicon layer at a reaction temperature between about 520&#xb0; C. and 560&#xb0; C.

Method for forming a gate structure through an amorphous silicon layer and applications thereof

Embodiments of the invention relate to a fabrication method of an electronic device, more particularly to a fabrication method of a power device in which an oxide layer at the bottom of the trench is provided to reduce Miller capacitance and further reduce RC delay. In one embodiment, a method for forming an oxide layer at the bottom of a trench comprises providing a first substrate with at least one trench therein; forming a first oxide layer on the bottom and sidewalls of the trench; removing the first oxide layer at the bottom of the trench; and forming a second oxide layer at the bottom of the trench.

Method for fabricating trench power device

A method for fabricating a trench isolation is disclosed. First, a first insulated layer having a void is formed within the trench of the semiconductor. Next, the upper portion of said first insulated layer is etched to remove the void of said first insulated layer. Then, a second insulated layer having a void is formed over the first insulated layer. Next, the upper portion of said second insulated layer is etched to remove the void of said second insulated layer, thereby forming a trench isolation including the remainder of said first and second insulated layers.

Method for fabricating a trench isolation

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Hsinchu, Taiwan

Tun-Fu Hung