International Business Machines Corporation

Tuhin Sinha

Jonathan R Fry

Taryn J Davis

Jeffrey Allen Zitz

Shidong Li

Kamal Kumar Sikka

Krishna R Tunga

Michael Rizzolo

Sushumna Iruvanti

Steven Paul Ostrander

Marcus E Interrante

Hilton T Toy

David L Questad

Thomas Anthony Wassick

Randall Jason Werner

Marek Andrzej Orlowski

Kathryn R Lange

Dureseti Chidambarrao

Charles Leon Arvin

Thomas Weiss

Naftali Eliahu Lustig

David S Wolpert

Brian W Quinlan

Kenneth Charles Marston

Michael S Gray

Atsushi Ogino

Sylvain E Ouimet

Matthew Thomas Guzowski

Bhupender Singh

Bassem M Hamieh

Max S Cioban

A chip package comprises a chip having a first temperature sensor. The first temperature sensor is configured to measure a first temperature of the chip in a localized area around the first temperature sensor. The chip package also includes a chip carrier coupled to the chip via a plurality of solder connections. The chip carrier includes a second temperature sensor vertically aligned with the first temperature sensor. The second temperature sensor is configured to measure a second temperature of the chip carrier in a localized area around the second temperature sensor. The chip carrier further includes a localized heater element located near the second temperature sensor and configured to generate heat in response to a detected difference based on comparison of the first temperature and the second temperature such that the detected difference is adjusted in the localized area around the first temperature sensor.

Fatigue failure resistant electronic package

A heat spreader is disclosed with regions where material is absent to reduce the mass/weight of the heat spreader without substantially reducing the temperature of the semiconductor chip and without substantially affecting the warpage and mechanical stress/strain in the electronic package.

Optimized weight heat spreader for an electronic package

A structure including a plurality of dielectric regions is described. The structure can include a rivet cell. The rivet cell can include a set of stacked vias. The rivet cell can extend through a stress hotspot of the structure. A length of the rivet cell can thread through at least one dielectric region among the plurality of dielectric regions. The rivet cell can be among a number of rivet cells inserted in the stress hotspot. The stress hotspot can be among a plurality of stress hotspots across the structure. A length of the rivet cell can be based on a model of a relationship between the length of the rivet cell and an energy release rate of the structure. The rivet cell can thread through an interface between a first dielectric region and a second dielectric region having different dielectric constants.

Stacked via rivets in chip hotspots

A multi-chip module (MCM) package includes an organic laminate substrate; first and second semiconductor device chips that are mounted to a top side of the substrate and that define a chip gap region between opposing edges of the chips; and a stiffener that is embedded in the bottom side of the substrate. The stiffener extends across a stiffening region, which underlies the chip gap region, and does not protrude beyond a bottom side metallization of the substrate.

Mitigating thermal-mechanical strain and warpage of an organic laminate substrate

An electronic apparatus that includes a first semiconductor chip mounted on a substrate; a second semiconductor chip mounted on the substrate; a spacer attached to the substrate and situated between the first and second semiconductor chips; a lid mounted on the substrate and enclosing the first and second semiconductor chips and the spacer, the spacer having an adhesive material adhesively attached to the lid; and underfill material underneath the first and second semiconductor chips, underneath the spacer and between the spacer and the first and second semiconductor chips.

Electronic apparatus having inter-chip stiffener

Embodiments of the present invention are directed to a new crack stop system and a method for providing an interlayer dielectric (ILD) crack bifurcation in semiconductor back-end-of-line (BEOL). In a non-limiting embodiment of the invention, a crack stop is formed over a substrate. The crack stop can span one or more dielectric layers. A topologically interlocking composite structure is formed adjacent to the crack stop and over the substrate. The topologically interlocking composite structure spans the one or more dielectric layers. A capping film is formed over the topologically interlocking composite structure and one or more metal interconnect layers are formed over the capping film. The composite structure includes a bulk matrix material and embedded inclusions. To promote crack bifurcation, materials of the inclusions and bulk matrix material are selected to ensure that the Young's modulus of the inclusions is greater than the Young's modulus of the bulk matrix material.

Crack bifurcation in back-end-of-line

A multi integrated circuit (IC) chip package includes multiple IC chips, a carrier, and a lid. The IC chips may be connected to the carrier. Alternatively, each IC chip may be connected to an interposer and multiple interposers may be connected to the carrier. The carrier may be positioned against a carrier deck. The lid may be positioned relative to carrier by aligning one or more alignment features within the lid with one or more respective alignment features of the carrier deck. A compression fixture cover may contact the lid and exert a force toward the carrier deck, the lid be loaded against respective IC chips, and the lid may be loaded against the carrier. While under compression, thermal interface material between respective the lid and respective IC chips and seal band material between the lid and the carrier may be cured.

Multi integrated circuit chip carrier package

A semiconductor device that includes a semiconductor substrate having a surface, the surface having several regions having different thermal and/or mechanical requirements; and a composite thermal interface material including several spatially localized thermal interface materials placed on the surface, each of the several thermal interface materials tailored to the different thermal and/or mechanical requirements of each of the regions. Also disclosed is a method of forming the composite thermal interface material.

Spatially localized thermal interface materials

A thermal interface material and systems and methods for forming a thermal interface material include depositing a layer of a composite material, including at least a first material and a second material, the first material including a carrier fluid and the second material including a filler particle suspended within the first material. A particle manipulator is positioned over the layer of the composite material, the particle manipulator including at least one emitter to apply a particle manipulating field to bias a movement of the filler particles. The second material is redistributed by applying the particle manipulating field to interact with the second material causing the second material to migrate from a surrounding region in the composite material into a high concentration region in the composite material to form a customized thermal interface such that the high concentration region is configured and positioned corresponding to a hotspot.

Filler particle position and density manipulation with applications in thermal interface materials

An integrated circuit (IC) device, such as a wafer, die, or the like, includes a viscoelastic pad upon a contact. The viscoelastic pad includes a viscoelastic material and an electrically conductive material within the viscoelastic material. The viscoelastic pad provides for a probe needle of an IC device tester to be electrically connected to the IC device contact without the probe needle directly contacting the IC device contact. The viscoelastic pad may be probed multiple instances by the probe needle and may be washed or otherwise removed from the IC device after testing is completed. The viscoelastic pad may be formed upon the IC device by forming the viscoelastic material within a mask, aligning the viscoelastic pad to the IC device contact, and ejecting the viscoelastic material from the mask upon the IC device contact.

Viscoelastic pad upon integrated circuit device contact for multipass electrical characterization probe testing

Embodiments of the present invention relate to an heterogenous thermal interface material (TIM). The heterogenous TIM includes two or more different materials. One material has a low elastic modulus, also known as Young's modulus, and is utilized primarily to transfer heat from one component to another component. Another material has a higher elastic modulus and is primarily utilized to bond or connect the corners and/or edges of one component to the other component. The high elastic modulus material is generally located within the heterogenous TIM where TIM strain is or is expected to be high. For example, the high elastic modulus material may be located at the corner and/or edge regions of the heterogenous TIM.

Heterogeneous thermal interface material for corner and or edge degradation mitigation

Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time without the need for destructive testing of the packages. The capacitive sensors can be used for flip-chip package reliability monitoring.

Method and structure for flip-chip package reliability monitoring using capacitive sensors groups

A method to control warpage in a semiconductor chip package that includes: attaching a semiconductor chip to a semiconductor chip package; attaching a stiffener to the semiconductor chip package so that the semiconductor chip is contained within the stiffener, the stiffener having a coefficient of thermal expansion (CTE) less than that of the substrate on which the chip is assembled; attaching the semiconductor chip package to a laminate substrate; and removing the stiffener.

Control warpage in a semiconductor chip package

A multi integrated circuit (IC) chip package includes multiple IC chips, a carrier, and a lid. The IC chips may be connected to the carrier. Alternatively, each IC chip may be connected to an interposer and multiple interposers may be connected to the carrier. The carrier may be positioned within a carrier deck. The lid may be positioned relative to carrier by aligning one or more alignment receptacles within the lid with one or more respective alignment protrusions of the carrier deck. A compression fixture cover may contact the lid and exert a force toward the carrier deck, respective lid pedestals may be loaded toward respective IC chips, and an integral lid foot may be loaded toward the carrier. While under compression, thermal interface material between respective lid pedestals and respective IC chips and seal band material between the integral foot and the carrier may be cured.

A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.

Growing community of inventors

Oradell, NJ, United States of America

Tuhin Sinha