Lsi Logic Corporation

Lst Corporation

Tuan L Phan

V Swamy Irrinki

William D Schwarz

Ghasi R Agrawal

Thomas R Wik

Mukesh K Puri

Thompson W Crosby

Thien Trieu

A BISR scheme which provides for on-chip assessment of the amount of repair on a given memory and for the flagging of any device as a fail when the device exceeds a pre-determined limit. Preferably, a counter is built and loaded through a test pattern during production testing, and the counter establishes the threshold for pass/fail criteria. The BISR is configured to load a repair solution and then test the memories for any additional failures and if there are any, repair them (provided enough redundant elements are available). In addition, a reliability controller for BISR designs can be provided, where the reliability controller contains a register set and a number of counters at the chip-level which can be loaded through a test pattern during production tests, where one of the counters contains the number of memories to be allowed for repair.

Hard BISR scheme allowing field repair and usage of reliability controller

A method and apparatus are disclosed for asynchronous testing of multiport memories. In one embodiment, the apparatus includes a built-in self-test (BIST) unit coupled to a multiport memory module and configured to apply a pattern of read and write test operations concurrently to multiple ports of the memory. The pattern of test operations may be any standard or customized pattern designed to establish the functionality of the multiport memory. The test operations to different ports are clocked by different clock signals so that the clock signals may be offset relative to each other by an adjustable or preset clock skew. Certain clock skews cause transitions to occur on signal lines in the memory array at the most sensitive portion(s) of a read cycle. The timing of these transitions, in combination with the presence of high-resistivity bridge faults, sufficiently disturbs the read cycle so as to cause a read error, thereby enabling detection of the bridge faults.

Asynchronous bist for embedded multiport memories

An integrated circuit includes built-in self test (BIST) and built-in self repair (BISR) circuitry, a fuse array capable of storing information related to defective memory locations identified during the manufacturing process. During manufacture, the integrity of the embedded memory of the integrated circuit is tested under a variety of operating conditions via the BIST/BISR circuitry. The repair solutions derived from these tests are stored and compiled in automated test equipment. If the repair solutions indicate that the embedded memory is repairable, the on-chip fuse array of the integrated circuit is programmed with information indicative of all of the detected defective memory locations. The built-in self repair circuitry of the integrated circuit is not executed upon power up. Instead, the repair information stored in the fuse array is provided to address remap circuitry within the BISR circuit. When an access to one of these memory locations is attempted during normal operation of the integrated circuit, the BISR circuitry remaps the memory operation to a redundant memory element.

Built-in self repair circuitry utilizing permanent record of defects

A system for disabling defective memory elements includes a memory array, an address decoder and a decoder element. The memory array has multiple memory elements for storing data. The address decoder receives a requested memory address and produces multiple element-select signals. Each element-select signal is associated with one of the memory elements and indicates whether access to the associated memory element is requested by the host. The decoder element receives one of the element-select signals and provides an output signal to the associated memory element. If the associated memory element is functional, the output signal enables or disables the associated memory element in accordance with the associated element-select signal. If, on the other hand, the associated memory element is defective, the output signal disables the associated memory element regardless of the associated element-select signal. The decoder element is programmed upon power-up so as not to require an address comparison for each memory access cycle.

Decoding circuit for memories with redundancy

A memory device configured to detect changes in fault patterns is disclosed. In one embodiment, the memory device includes a memory array, a built-in self-test (BIST) unit, and a built-in self-repair (BISR) unit. The BIST unit runs test patterns on the memory array to identify faulty locations in the array. A comparator within the BIST or external to the BIST compares the actual output of the memory array to the expected output, and asserts an error signal whenever a mismatch occurs. The BISR unit intercepts addresses directed to the memory array, and operates on the addresses in three distinct phases. During a training phase, the BISR unit stores the intercepted addresses when the error signal is asserted. During the normal operation phase, the BISR unit compares all intercepted addresses to stored addresses and redirects a corresponding memory access if any intercepted address matches a stored address. During a verification phase, the BISR unit compares intercepted addresses designated by assertions of the error signal to the addresses previously stored in the training phase. If the faulty intercepted address fails to match a stored address, the BISR unit asserts a &ldquo;new error&rdquo; signal. If at the end of the verification phase, a stored address has not matched nay intercepted faulty address, the BISR asserts a &ldquo;missed error&rdquo; signal.

Multi-condition BISR test mode for memories with redundancy

A low-complexity method and apparatus for generating address sequences for the moving inversion test method. In one embodiment, the address sequence generator includes a ring of counter cells in which each cell is configured to provide a toggle signal to a subsequent cell. Each cell receives a distinct least significant bit selector signal which, when asserted, designates the subsequent cell as the least significant bit. When the least significant selector signal is asserted, the cell continuously asserts the toggle signal to the subsequent cell. When the selector signal is de-asserted, the cell asserts the toggle signal to the subsequent cell half as often as the toggle signal from the preceding cell. Each cell provides an output address bit which is toggled whenever the toggle signal from the preceding bit is asserted across a transition in a clock signal. This configuration causes the ring of cells to implement a counter with a selectable least significant bit. As discussed herein, each cell may be implemented using only a toggle flip-flop and two logic gates. The addition of a direction signal and a third logic gate per cell makes the address sequencer bi-directional.

Programmable moving inversion sequencer for memory bist address generation

A method for improving the fault coverage of manufacturing tests for integrated circuits having structures such as embedded memories. In the disclosed embodiment of the invention, the integrated circuit die of a semiconductor wafer are provided with a fuse array or other circuitry capable of storing an identification number. The integrated circuit die also include an embedded memory or similar circuit and built-in self-test (BIST) and built-in self-test (BISR) circuitry. At a point early in the manufacturing test process, the fuse array of each integrated circuit die is encoded with an identification number to differentiate the die from other die of the wafer or wafer lot. The integrity of the embedded memory of each integrated circuit die is then tested at the wafer level under a variety of operating conditions via the BIST and BISR circuitry. The results of these tests are stored in ATE and associated with a particular integrated circuit die via the identification number of the die. The manufacturing test process then continues for the packaged integrated circuits. As with the unsingulated die, the packaged parts are subjected to one or more sets of stress factors, with data being gathered at each stage. Again, test results (e.g., faulty memory locations as determined by the BIST circuitry) are correlated to specific packaged parts via the identification number of the integrated circuit die. The test results of the various stages are next compared to determine if any detected repairable failures are uniform across the various operating conditions. In general, the assumption is made that an integrated circuit IC which exhibits different failure mechanisms at different stages of the testing/manufacturing process is questionable and the part is discarded.

Testing methodology for embedded memories using built-in self repair and identification circuitry

Accordingly, there is disclosed herein a fast word compare circuit suitable for use in a BIST or BISR environment. In one embodiment, the comparator includes a front end and a zero-detector circuit. The front end receives two or more words and compares them bitwise, generating a set of bit match signals that indicate which bits match. The zero detector receives the bit match signals from the front end and asserts an output signal when all the bit match signals indicate a match. The front end may consist of a set of exclusive-or (XOR) gates, each configured to generate a bit match signal from respective bits of the input words. The zero detector may include a set of bit transistors coupled in parallel between a first node and ground. Each bit transistor receives a respective bit match signal and conducts when the respective bit match signal is asserted. A first clock transistor may be coupled between the first node and a second node and configured to conduct when a clock signal is asserted, and a second clock transistor may be coupled between a positive source voltage and the second node and configured to conduct when the clock signal is de-asserted. If a pull-up resistance is provided, this allows the first or second node to indicate the match or mismatch of the input words. Further robustness may be provided by a Schmitt-trigger configuration coupled to the second node.

Fast comparator suitable for BIST and BISR applications

An information circuit in a semiconductor device suitable for encoding and retrieving a bit of information. The information circuit includes an input circuit and an output circuit. The input circuit includes an input node coupled to an input terminal of a transistor. The output circuit includes a load device, a fuse circuit, and first and second output terminals of the transistor all coupled in series between a power supply terminal and a ground terminal. The impedance of said fuse circuit is preferably alterable between an initial impedance and an altered impedance. An output node of said information circuit is coupled to said output circuit. The information circuit is configured such that the output node voltage is indicative of said impedance of said fuse circuit when said input node is biased to a &ldquo;read&rdquo; state, said power supply terminal is biased to a power supply voltage, and said ground terminal is grounded.

Circuit and method for encoding and retrieving a bit of information

An efficient methodology for detecting and rejecting faulty integrated circuits with embedded memories utilizing stress factors during the manufacturing production testing process. In the disclosed embodiment of the invention, a stress factor is applied to an integrated circuit having built-in-self-test (BIST) circuitry and built-in-self-repair (BISR) circuitry. A BIST run is then performed on a predetermined portion of the integrated circuit to detect a set of faulty memory locations. The results of this first BIST run are stored. A second condition is applied to the die and a second BIST run is executed to generate a second set of faulty memory locations. The results of the second BIST run are stored and compared with the first result. If the results differ, the integrated circuit is rejected. Thus, a methodology for screening out field errors at the factory is disclosed using BIST/BISR circuitry.

Redundancy analysis for embedded memories with built-in self test and

A method for testing refresh operations of a memory array wherein subthreshold leakage current may be set to near worst-case conditions. The memory array includes a first row of memory cells having a first memory cell configured to store a first memory value, and a second row of memory cells having a second memory cell configured to store a second memory value. The method comprises storing a logic high value to the first memory cell as the first memory value, followed by storing a logic low value to the second memory cell as the second memory value. The method further comprises repeatedly driving a write bit line coupled to both the first and second memory cells at a logic low level for a period of a time equal to a refresh interval corresponding to the first memory cell. Additionally, the method includes subsequently reading the first memory value from the first memory cell. Finally, the method includes indicating that the first memory cell is operating correctly if the first memory value is still equal to a logic high value, or indicating that the first memory value is malfunctioning if the first memory value is equal to a logic low value. Driving the write bit line low may be accomplished by repetitively reading the second memory cell. The same effect may alternately be achieved by repetitively writing a logic low value to the second memory cell. By keeping the write bit line at a logic low level during testing of refresh operations, the subthreshold leakage current through the write transistor of the first memory cell may be increased. This accelerates the discharge of the first memory value, and insures testing is performed near worst-case conditions.

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San Jose, CA, United States of America

Tuan L Phan