International Business Machines Corporation

Globalfoundries Inc.

Canon Anelva Corporation

Tuan Anh Vo

Wei Lin

Spyridon Skordas

Son Van Nguyen

Deepika Priyadarshini

Daniel C Edelstein

Vamsi Krishna Paruchuri

Christopher Joseph Waskiewicz

James John Kelly

Douglas C La Tulipe, Jr

Kevin R Winstel

Alfred Grill

Soon-Cheon Seo

Hosadurga K Shobha

Thomas J Haigh, Jr

Juntao Li

Veeraraghavan S Basker

Yunpeng Yin

Paul Charles Jamison

Balasubramanian S Pranatharthi Haran

Bala S Haran

Takaaki Tsunoda

Sanjay Shinde

Veeraghavan S Basker

Bryan G Morris

A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.

Substrate bonding with diffusion barrier structures

A semiconductor assembly for use with forced liquid and gas cooling. A relatively rigid nano-structure (for example, array of elongated nanowires) extends from an interior surface of a cap toward a top surface of a semiconductor chip, but, because of the rigidness and structural integrity of the nano-structure built into the cap, and of the cap itself, the nano-structure is reliably spaced apart from the top surface of the chip, which helps allow for appropriate cooling fluid flows. The cap piece and nano-structures built into the cap may be made of silicon or silicon compounds.

Semiconductor package with structures for cooling fluid retention

An interconnect structure is provided that has improved electromigration resistance as well as methods of forming such an interconnect structure. The interconnect structure includes a composite M-MOx cap located at least on the upper surface of the Cu-containing material within the at least one opening. The composite M-MOx cap includes an upper region that is composed of the metal having a higher affinity for oxygen than copper and copper oxide and a lower region that is composed of a non-stoichiometric oxide of said metal.

Method of forming an interconnect structure

A manganese oxide layer is deposited as a hard mask layer on substrate including at least a dielectric material layer. An optional silicon oxide layer may be formed over the manganese oxide layer. A patterned photoresist layer can be employed to etch the optional silicon oxide layer and the manganese oxide layer. An anisotropic etch process is employed to etch the dielectric material layer within the substrate. The dielectric material layer can include silicon oxide and/or silicon nitride, and the manganese oxide layer can be employed as an effective etch mask that minimizes hard mask erosion and widening of the etched trench. The manganese oxide layer may be employed as an etch mask for a substrate bonding process.

Manganese oxide hard mask for etching dielectric materials

An apparatus and method bond a first wafer to a second wafer. The apparatus includes a first pressure application device configured to apply pressure at a central region of the first wafer in a direction toward the second wafer to initiate a bonding process between the first wafer and the second wafer. The apparatus also includes one or more second pressure application devices configured to apply pressure between the central region and an outer edge of the first wafer to complete the bonding process. The one or more second pressure application devices apply pressure on the first wafer after the first pressure application device has initiated the bonding process and while the first pressure application device continues to apply pressure at the central region. A controller controls the first pressure application device and the one or more second pressure application devices.

Wafer bonding for 3D device packaging fabrication

Liquid cooling of semiconductor chips utilizing small scale structures

A vertical stack including a dielectric hard mask layer and a titanium nitride layer is formed over an interconnect-level dielectric material layer such as an organosilicate glass layer. The titanium nitride layer may be partially or fully converted into a titanium oxynitride layer, which is subsequently patterned with a first pattern. Alternately, the titanium nitride layer, with or without a titanium oxynitride layer thereupon, may be patterned with a line pattern, and physically exposed surface portions of the titanium nitride layer may be converted into titanium oxynitride. Titanium oxynitride provides etch resistance during transfer of a combined first and second pattern, but can be readily removed by a wet etch without causing surface damages to copper surfaces. A chamfer may be formed in the interconnect-level dielectric material layer by an anisotropic etch that employs any remnant portion of titanium nitride as an etch mask.

Titanium oxynitride hard mask for lithographic patterning

Improving wafer-to-wafer bonding alignment. Determining planar distortions of the bonding surface of a host wafer. Mounting a donor wafer on a bonding chuck by a plurality of fixation points, the bonding chuck including multiple zones capable of movement relative to each other. Distorting the bonding surface of the donor wafer by moving the zones of the bonding chuck relative to each other to cause distortions of the bonding surface of the donor wafer such that the distortions of the donor wafer bonding surface correspond to the determined planar distortions of the host wafer bonding surface.

Distorting donor wafer to corresponding distortion of host wafer

A method of producing reduced corrosion interconnect structures and structures thereby formed. A method of producing microelectronic interconnects having reduced corrosion begins with a damascene structure having a first dielectric and a first interconnect. A metal oxide layer is deposited selectively to metal or nonselective over the damascene structure and then thermally treated. The treatment converts the metal oxide over the first dielectric to a metal silicate while the metal oxide over the first interconnect remains as a self-aligned protective layer. When a subsequent dielectric stack is formed and patterned, the protective layer acts as an etch stop, oxidation barrier and ion bombardment protector. The protective layer is then removed from the patterned opening and a second interconnect formed. In a preferred embodiment the metal oxide is a manganese oxide and the metal silicate is a MnSiCOH, the interconnects are substantially copper and the dielectric contains ultra low-k.

Corrosion/etching protection in integration circuit fabrications

Embodiments include methods of forming dielectric layers. According to an exemplary embodiment, a dielectric layer may be formed by determining a desired thickness of the dielectric layer, forming a first dielectric sub-layer having a thickness less than the desired thickness by depositing a first metal layer above a substrate and oxidizing the first metal layer, and forming n (where n is greater than 1) additional dielectric sub-layers having a thickness less than the desired thickness above the first dielectric sub-layer by the same method of the first dielectric sub-layer so that a combined thickness of all dielectric sub-layers is approximately equal to the desired thickness.

Cyclical physical vapor deposition of dielectric layers

Oxide-oxide fusion bonding of wafers that includes performing a van der Waals force bonding process with a chuck having at least a flat central zone and an outer annular zone lower than the central zone, an edge portion of a mounted wafer is biased towards the outer annular zone. The van der Waals bonding wave is disrupted at the outer annular zone, causing an edge gap. A thermocompression bonding process is performed that includes heating the bonded wafers to a temperature sufficient to initiate condensation of silanol groups between the bonding surfaces, reducing the atmospheric pressure to cause degassing from between the wafers, applying a compression force to the wafers with flat chucks so as to substantially eliminate the edge gap, and performing a permanent anneal bonding process.

Wafer-to-wafer oxide fusion bonding

A lithographic material stack including a metal-compound hard mask layer is provided. The lithographic material stack includes a lower organic planarizing layer (OPL), a dielectric hard mask layer, and the metal-compound hard mask layer, an upper OPL, an optional anti-reflective coating (ARC) layer, and a photoresist layer. The metal-compound hard mask layer does not attenuate optical signals from lithographic alignment marks in underlying material layers, and can facilitate alignment between different levels in semiconductor manufacturing.

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Albany, NY, United States of America

Tuan Anh Vo