Freescale Semiconductor,inc.

Nxp Usa, Inc.

Tu-Anh N Tran

Chu-Chung Lee

Burton Jesse Carpenter

Kevin John Hess

Peter R Harper

Susan H Downey

Sohrab Safai

James W Miller

Sheila F Chopin

Heng Keong Yip

Alan H Woosley

David Clegg

James Patrick Johnston

Kian Leong Chin

Perry H Pelley

Leo M Higgins, Iii

Richard Eguchi

Varughese Mathew

Kurt H Junker

Yaping Zhou

William M Williams

Yuan Yuan

Chin Teck Siong

Nhat Dinh Vo

Yin Kheng Au

Meijiang Song

Jia Lin Yap

Lois E Yong

Patrick Johnston

Kendall Dewayne Phillips

Dae Y Hong

Michael V Leoni

John G Arthur

Matthew J Zapico

Donna Woosley, Legal Representative

The present disclosure provides embodiments of package devices and methods for making package devices for a semiconductor die. One embodiment includes a die mounting structure having a finished bond pad that includes a copper bond pad and a cobalt-containing layer over a top surface of the copper bond pad, and a wire bond structure that is bonded to a top surface of the cobalt-containing layer of the finished bond pad, where cobalt-containing material of the cobalt-containing layer is located between a bottom surface of the wire bond structure and the top surface of the copper bond pad such that the cobalt-containing material is present under a center portion of the wire bond structure.

Surface finish for wirebonding

A method for forming a semiconductor structure includes forming a bond pad over a last metal layer of the semiconductor structure wherein the bond pad includes a wire bond region; and recessing the wire bond region such that the wire bond region has a first thickness and a region of the bond pad outside the wire bond region has a second thickness that is greater than the first thickness.

Methods for forming semiconductor devices with stepped bond pads

A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a selected portion of the passivation material. The selected portion represents a bond region of a wire bond to be formed above the passivation material. A portion of the passivation material completely covers a bottom of the trench. A layer of conductive material is conformally deposited over the passivation material. The conformal depositing resulting in a second trench forming in the conductive material over the first trench in the passivation material. The second trench is positioned to contain at least a portion of a splash of the conductive material when the wire bond is subsequently formed.

Bond pad having a trench and method for forming

An electronic component package that includes a package substrate having an aluminum bond pad formed from an aluminum clad copper structure. The aluminum clad copper structure is attached to a dielectric layer. An electronic component is attached to the substrate and includes a conductive structure electrically coupled to the aluminum bond pad. The aluminum bond pad, the electronic component, and at least a portion of the substrate are encapsulated with an encapsulant.

Aluminum clad copper structure of an electronic component package and a method of making an electronic component package with an aluminum clad copper structure

An electronic component package includes a substrate and dielectric structure. The dielectric structure includes a top surface having a protrusion portion and a lower portion. The protrusion portion is located at first height that is greater than a second height of the lower portion. A conductive bond pad is located over the dielectric structure. A ball bond electrically couples the bond pad and a bond wire. An intermetallic compound located between the ball bond and bond pad is formed of material of the ball bond and bond pad and electrically couples the bond pad to the ball bond. A portion of the bond pad is vertically located between a portion of the lower portion of the top surface of the dielectric structure and the intermetallic compound. No portion of the bond pad is vertically located between at least a portion of the protrusion portion and the intermetallic compound.

Electronic component package and method for forming same

A semiconductor device includes a bond formed on a bond pad. The bond is formed of a wire that includes a central core of conductive metal, a first coating over the central core of conductive metal that is more chemically active than the conductive metal, and a second coating over the central core of conductive metal that is less chemically active than the central core of conductive metal.

Coated bonding wire and methods for bonding using same

An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.

Integrated circuit package with voltage distributor

A semiconductor structure includes a bond pad and a wire bond coupled to the bond pad. The wire bond includes a bond in contact with the bond pad. The wire bond includes a coating on a surface of the wire bond, and a first exposed portion of the wire bond in a selected location. The wire bond is devoid of the coating over the selected location of the wire bond, and an area of the first exposed portion is at least one square micron.

Structures for reducing corrosion in wire bonds

An integrated circuit copper wire bond connection is provided having a copper ball () bonded directly to an aluminum bond pad () formed on a low-k dielectric layer () to form a bond interface structure for the copper ball characterized by a first plurality of geometric features to provide thermal cycling reliability, including an aluminum minima feature (Z1, Z2) located at an outer peripheral location () under the copper ball to prevent formation and/or propagation of cracks in the aluminum bond pad.

Copper ball bond interface structure and formation

A semiconductor device comprises an integrated circuit including a wire bond pad and a passivation material, and a first gap between a first selected portion of the wire bond pad and the passivation material. The first gap is positioned to contain at least a first portion of a splash of the wire bond pad formed during a wire bond process.

Bond pad and passivation layer having a gap and method for forming

Forming an embedded electronic component includes attaching an electronic component to a first conductive layer and forming a layer stack with a first partially cured dielectric layer having a first opening and a substrate having a second opening. The partially cured dielectric layer is located over the first conductive layer and the substrate is located over the first partially cured dielectric layer such that the first and second openings surround the electronic component. Heat and pressure are applied to the layer stack such that the first partially cured dielectric layer flows for filling gaps within the first and second openings and becomes fully cured.

Embedded electronic component

A packaging assembly (), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die () by using an encapsulated patterned leadframe conductor () that is disposed over the die () and bonded to a plurality of bonding pads () formed in a BGA carrier substrate () and in the interior die region, thereby electrically coupling the interior die region to an externally provided reference voltage.

Power lead-on-chip ball grid array package

A pad () is electrically connected to a first I/O cell () while also physically overlying active circuitry of a second I/O cell (). Note that although the pad () overlies the second I/O cell (), the pad () is not electrically connected to the I/O cell (). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g.-) may have a finer pitch than the corresponding pads (-and-). In addition, the size of the pads may be increased (e.g. padmay be bigger than pad) while the width 'c' of the I/O cells (-) does not have to be increased. Such a pattern (e.g.) may be arranged so that the area required in one or more dimensions may be minimized.

Integrated circuit having pads and input/output (I/O) cells

An integrated circuit has a semiconductor substrate and an interconnect layer that mechanically relatively weak and susceptible to cracks and delamination. In the formation of the integrated circuit from a semiconductor wafer, a cut is made through the interconnect layer to form an edge of the interconnect layer. This cut may continue completely through the wafer thickness or stop short of doing so. In either case, after cutting through the interconnect layer, a reconditioning layer is formed on the edge of the interconnect layer. This reconditioning layer seals the existing cracks and delaminations and inhibits the further delamination or cracking of the interconnect layer. The sealing layer may be formed, for example, before the cut through the wafer, after the cut through the wafer but before any packaging, or after performing wirebonding between the interconnect layer and an integrated circuit package.

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Austin, TX, United States of America

Tu-Anh N Tran