Cadence Design Systems, Inc.

Tsuwei Ku

Jean-Charles Giomi

Ankush Sood

Kai Zhu

David John Seibert

Yu-Fang Chung

Samir Agrawal

Huey-Yih Wang

Hua Song

In one embodiment of the invention, a method of logic synthesis is disclosed. The method includes generating a plurality of design architecture alternatives for circuit logic of a data path cluster; saving the plurality of design architecture alternatives; and evaluating the plurality of design architecture alternatives in response to design constraints to select a preferred design architecture.

Methods and apparatus for data path cluster optimization

In one embodiment of the invention, a method of synthesizing physical gates from register transfer logic code for an integrated circuit design is disclosed. The method includes reading a register transfer level (RTL) input file describing an integrated circuit design; parsing and translating the RTL input file into a plurality of Boolean logic equations; translating the plurality of Boolean logic equations into a plurality of logic primitives; placing the plurality of logic primitives into a floorplan of the integrated circuit design, wherein the placement of the plurality of logic primitives defines wire interconnects; and optimizing each of the plurality of Boolean logic equations in response to wire costs and wire timing delays.

Physically aware logic synthesis of integrated circuit designs

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Cupertino, CA, United States of America

Tsuwei Ku