Kabushiki Kaisha Toyota Chuo Kenkyusho

Toyota Jidosha Kabushiki Kaisha

Denso Corporation

Rensselaer Polytechnic Institute

Tsutomu Uesugi

Tetsu Kachi

Masahiro Sugimoto

Hiroyuki Ueda

Narumasa Soejima

Sachiko Kawaji

Masahito Kodama

Yoshitaka Nakano

Takashi Suzuki

Masakazu Kanechika

Kenji Ito

Norihito Tokura

Kazuyoshi Tomita

Shinichi Hoshi

Toshio Murata

Shoji Mizuno

Tetsuo Narita

Masayasu Ishiko

Yoshinori Tsuchiya

Tat-Sing Chow

Kenji Itoh

Daigo Kikuta

Osamu Ishiguro

Zhongda Li

A semiconductor device may include: a semiconductor layer; and a trench gate. The semiconductor layer may include: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type provided above the first semiconductor region and facing a side surface of the trench gate; and a third semiconductor region of the first conductive type provided above the second semiconductor region, separated from the first semiconductor region by the second semiconductor region, and facing the side surface of the trench gate. The first semiconductor region may include: a lower semiconductor region; and an upper semiconductor region disposed between the lower semiconductor region and the second semiconductor region and having a lower impurity concentration than the lower semiconductor region. The upper semiconductor region may be disposed at a shallower position than the trench gate and face the side surface of the trench gate.

Power semiconductor device

A semiconductor device includes a switching device having: a substrate configured by a semi-insulating material or a semiconductor; a channel forming layer on the substrate that is configured by a compound semiconductor mainly having a group III nitride; a gate structure configured by a gate electrode on the channel forming layer with a gate insulating film interposed therebetween; and a source electrode and a drain electrode on the channel forming layer at both sides of the gate structure respectively, a collapse inhibiting layer on the channel forming layer in an element region of the channel forming layer where the switching device is arranged that is configured by an insulating material; and a leakage inhibiting layer on the channel forming layer in an element isolation region of the channel forming layer surrounding the element region that is configured by an insulating material different from that of the collapse inhibiting layer.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a HEMT and a diode. The HEMT includes: a substrate having a GaN layer as a channel layer generating a two-dimensional electron gas and an AlGaN layer as a barrier layer on the GaN layer; a source electrode on the AlGaN layer ohmic contacting the AlGaN layer; a drain electrode on the AlGaN layer apart from the source electrode and ohmic contacting the AlGaN layer; an inter-layer insulating film on the AlGaN layer between the source electrode and the drain electrode; and a gate electrode on the inter-layer insulating film. The substrate includes an active layer region generating the two dimensional electron gas in the GaN layer. The diode includes an anode electrically connected to the gate electrode and a cathode electrically connected to the drain electrode.

Semiconductor device with high electron mobility transistor

A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1&#xd7;10cm. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.

III-V HEMT devices

A semiconductor device is provided with an electronic transit layer, an electron supply layer, a source region, a drain electrode, a source electrode and an insulated gate. In a region between the drain electrode and the insulated gate, a two-dimensional electron gas layer is configured to be generated at a hetero junction between the electronic transit layer and the electron supply layer. A part of the insulated gate is configured to face to the source region.

Semiconductor device

A semiconductor deviceis provided with a first hetero junctionconfigured with two types of nitride semiconductors having different bandgap energy from each other, a second hetero junctionconfigured with two types of nitride semiconductors having different bandgap energy from each other, and a gate electrodefacing the second hetero junction. The second hetero junctionis configured to be electrically connected to the first hetero junction. The first hetero junctionis a c-plane and the second hetero junctionis either an a-plane or an m-plane.

Semiconductor device having hetero junction

A nitride semiconductor devicecomprises a nitride semiconductor layer. A gate insulating filmis formed on the surface of the nitride semiconductor layer. The gate insulating filmincludes a portion composed of an aluminum nitride filmand a portion composed of an insulating materialthat contains at least one of oxygen or silicon. A region Wof the nitride semiconductor layerfacing the aluminum nitride filmis included in a region Wof the nitride semiconductor layerfacing a gate electrode. The nitride semiconductor devicemay further comprise a nitride semiconductor lower layer. The nitride semiconductor layermay be stacked on the surface of the nitride semiconductor lower layer. The nitride semiconductor layermay have a larger band gap than that of the nitride semiconductor lower layerand have a heterojunction formed there between.

Nitride semiconductor device including gate insulating portion containing AIN

An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway.

Transistor

A semiconductor device has a semiconductor substrate having a surface layer and a p-type semiconductor region, wherein the surface layer includes a contact region, a channel region and a drift region, the channel region is adjacent to and in contact with the contact region, the drift region is adjacent to and in contact with the channel region and includes n-type impurities at least in part, and the p-type semiconductor region is in contact with the drift region and at least a portion of a rear surface of the channel region, a main electrode disposed on the surface layer and electrically connected to the contact region, a gate electrode disposed on the surface layer and extending from above a portion of the contact region to above at least a portion of the drift region via above the channel region, and an insulating layer covering at least the portion of the contact region and not covering at least the portion of the drift region. The gate electrode and the contact region are insulated by the insulating layer, and the gate electrode and the drift region are in direct contact to form a Schottky junction.

A semiconductor device is provided with a drain electrode, a semiconductor base plate, an electric current regulation layercovering a part of a surface of the semiconductor base plateand leaving a non-covered surfaceat the surface of the semiconductor base plate, a semiconductor layercovering a surface of the electric current regulation layer, and a source electrodeformed at a surface of the semiconductor layer. A drift region, a channel forming region, and a source regionare formed within the semiconductor layer. The drain electrodeis connected to a first terminal of a power source, and the source electrodeis connected to a second terminal of the power source. With this semiconductor layer, it is possible to increase withstand voltage or reduce the occurrence of current leakage.

Semiconductor device having vertical electrodes structure

A semiconductor devicecomprises a heterojunction between a lower semiconductor layermade of p-type gallium nitride and an upper semiconductor layermade of n-type AlGaN, wherein the upper semiconductor layerhas a larger band gap than the lower semiconductor layer. The semiconductor devicefurther comprises a drain electrodeformed on a portion of a top surface of the upper semiconductor layer, a source electrodeformed on a different portion of the top surface of the upper semiconductor layer, and a gate electrodeelectrically connected to the lower semiconductor layer. The semiconductor devicecan operate as normally-off.

Semiconductor devices

III-V hemt devices

A semiconductor device is formed by a first layercomposed of AlGaN, a second layercomposed of GaN, a gate electrode, a source electrode, and a drain electrode. The first layerhas a regionformed between the gate electrodeand the second layer. A channel is formed in the vicinity of the boundaryof the first layerand the second layer. The second layerhas p-type conductivity and is in contact with the source electrode When electrons flow in the channel, the electrons collide with surrounding atoms, and holes are formed. If holes are accumulated inside the semiconductor device, the presence of the accumulated holes causes dielectric breakdown. In the semiconductor device of the invention, holes are discharged to the outside of the device thorough the second layerand the source electrode, and accumulation of holes can be prevented.

Group III nitride semiconductor device

A vertical type MOS field effect transistor has a super junction structure between a source electrode and an N-type drain region. The super junction structure is constituted by a plurality of P-type single crystal silicon regions and a plurality of N-type single crystal silicon regions. Each of the plurality of P-type single crystal silicon regions and each of the plurality of N-type single crystal silicon regions are arrayed alternately. The super junction has two parts, that is, a cell forming region where a MOS structure is disposed and a peripheral region located at a periphery of the cell forming region. The source electrode contacts one of the P-type single crystal silicon regions in the peripheral region while disposed away from an end portion of the peripheral region that is located at an outermost in the peripheral region.

Growing community of inventors

Seto, Japan

Tsutomu Uesugi