Sharp Kabushiki Kaisha Corporation

Tsutomu Ashida

Yasumori Fukushima

Jun Kudo

Katsumasa Fujii

Yasuo Torimaru

Mikiro Okada

Kiyotoshi Nakagawa

A method for fabricating a semiconductor device, comprising the steps of: forming an element on a silicon substrate; packaging the element; and annealing the packaged element before its transportation or long-term storage.

Method for fabricating semiconductor device

An integrated CMOS semiconductor circuit comprises: an internal circuit composed of CMOS transistors including P3- and N-channel transistors each having a gate electrode and source/drain regions formed on a semiconductor substrate, the internal circuit functioning in at least two states including an active state in which data is input and output, and a standby state in which a state of the internal circuit is maintained; an external circuit composed of any electrical element and provided with a power source; and a switch portion which is enable to apply, in the standby state in the internal circuit, a reverse bias between the source and the substrate of either one of the P- and N-channel transistors of the internal circuit by the power source of the external circuit.

CMOS semiconductor circuit with reverse bias applied for reduced power consumption

There is provided a quantum thin line producing method capable of forming a quantum thin line that has good surface flatness of silicon even after formation of quantum thin line and a complete electron confining region with good controllability as well as a semiconductor device employing the quantum thin line. A region of a nitride film which covers a semiconductor substrate on which a stepped portion is formed is etched back with masking, consequently exposing an upper portion of a semiconductor substrate . Next, an oxide film is formed by oxidizing the exposed portion of the upper portion of the semiconductor substrate , and a linear protruding portion is formed on the semiconductor substrate along a side surface of the nitride film . Next, the oxide film on the protruding portion is partially etched to expose a tip of the protruding portion . Next, a thin line portion is made to epitaxially grow on the exposed portion at the tip of the protruding portion . Then, after removing the nitride film and the oxide film , there is formed a quantum thin line that is insulated and isolated from the semiconductor substrate by an oxide film A formed through oxidation of the semiconductor substrate

Quantum thin line producing method and semiconductor device employing the quantum thin line

A memory cell is formed in which N channel transistors A and P channel transistors B having respectively different conduction types are alternately fitted. The channel section of the N channel transistor A and the P-type drain,of the P channel transistor B are commonly used in a shared manner, and the channel section of the P channel transistor B and the N-type source,of the N channel transistor A are commonly used in a shared manner; thus, it is possible to achieve high integrity. Moreover, the junction between the adjacent P-type drain,and N-type source,is always maintained in a reverse bias state so that the P-type drain,and the N-type source,are separated. With this arrangement, the separation area between the respective transistor elements is minimized so that it is possible to provide a semiconductor device which can achieve miniaturization and high integrity.

Semiconductor device

A semiconductor device is provided which comprises: a semiconductor chip having a semiconductor substrate, an insulation a film, a field oxide film and pads formed on a surface thereof; bumps respectively formed on the pads; inner leads bonded to the semiconductor chip with intervention of bumps; a metal interconnection formed in an indentation which is formed between the pads and an edge of the semiconductor chip by removing part of the insulation film and/or the field oxide film of the semiconductor chip; and a pair of dummy electrodes respectively formed between each of the pads and the metal interconnection and between the metal interconnection and the edge of the chip at a higher elevation than the metal interconnection and spaced apart a predetermined distance from the metal interconnection, the pair of dummy electrodes being provided for each of the inner leads, which is located thereabove.

Semiconductor device with a pair of dummy electrodes below an inner lead

A nonvolatile semiconductor memory device comprises a memory cell array and a redundant circuit. The memory cell array comprises a plurality of cell lines for storing fixed data. The redundant circuit comprises redundancy memory cell rows of MOS transistors, and at least one redundancy spare decoder by which at least one of the redundancy memory cell rows is selectively determined and permuted with a memory cell to be repaired. At least one of the redundancy memory cell rows has data to be recovered stored therein. The data to be recovered is stored in the redundancy memory cell rows by selectively implanting channel regions of the memory cell rows with an impurity ion of high energy.

Semiconductor memory device with redundancy structure and process of

A matrix type semiconductor memory device with a higher complexity is provided which includes a p-type (or an n-type) semiconductor substrate, a plurality of n-type (or p-type) semiconductor regions formed as strips that are arranged in parallel at predetermined spacings in the surface of the substrate, the semiconductor regions provide alternating source regions and drain regions which define gate regions between the alternating regions, a first gate insulating film formed in a plurality of strips on the surface of the substrate at predetermined spacings which intersect the plurality of semiconductor regions, a plurality of first gate electrodes formed on each of the strips of the first gate insulating film, a second gate insulating film formed in a plurality of portions on the exposed surfaces of the substrate between the strips of first gate insulating film, and a plurality of second gate electrodes formed on each of the portions of the second gate insulating film without contacting the first gate electrodes. Thereby, a matrix of MIS semiconductor cells is formed, with each of the cells being provided at the intersection of each of the gate regions with one of the first and second electrodes, and the gate regions of some of the cells are selectively doped with a p-type (or an n-type) impurity substance at a higher concentration than the substrate.

Semiconductor memory device with compact ROM memory cells

A metal oxide semiconductor device is featured by the provision of a covering element for covering a channel region of the semiconductor device there being interposed therebetween an insulating layer. The covering element is connected to at least one electrode selected from the drain electrode, the source electrode and the gate electrode. Therefore, the electrical level of the covering element is fixed.

Growing community of inventors

Yamatokoriyama, Japan

Tsutomu Ashida