Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsung-Yen Lee

Po-Chung Cheng

Tzung-Chi Fu

Po-Yao Lin

Shin-Puu Jeng

Chin-Hua Wang

Ming-Chih Yew

Ching-Juinn Huang

Li-Jui Chen

Che-Chang Hsu

Chueh-Chi Kuo

Po-Chen Lai

Hsiao-Lun Chang

Hao-Yu Lan

Shu-Shen Yeh

Chia-Kuei Hsu

Siao-Chian Huang

Kuang-Chun Lee

Li-Ling Liao

Chia-Hsin Chou

Jui-Ching Wu

Shang-Lun Tsai

Jeng-Horng Cheng

A particle removal apparatus is provided. The apparatus includes a reticle holder configured to hold a reticle, a robotic arm, and a particle removal device disposed on the robotic arm. The particle removal device includes a solution spraying module, a sucking module, and a baffle. The robotic arm and the particle removal device are configured to align with a particle on the backside of the reticle. The solution spraying module is configured to spray a solution onto the particle to remove the particle. The baffle is configured to be disposed over the backside of the reticle to define enclosed area that encompasses the particle to be removed. The sucking module is configured to suck the solution on the reticle with the particles being removed.

Particle removal apparatus

A chip package structure is provided. The chip package structure includes a first semiconductor die bonded over an interposer substrate and a warpage release layer structure. The chip package structure also includes a first organic material layer covering an upper surface of the first semiconductor die; and a first metal layer covering an upper surface of the first organic material layer. The first metal layer has a planar shape that is the same as a planar shape of the first semiconductor die, as viewed in a top-view perspective.

Semiconductor die with warpage release layer structure in package and fabricating method thereof

A package structure including an organic interposer substrate, a semiconductor die, conductive bumps, an underfill, and an insulating encapsulation is provided. The organic interposer substrate includes stacked organic dielectric layers and conductive wirings embedded in the stacked organic dielectric layers. The semiconductor die is disposed over and electrically connected to the conductive wirings of the organic interposer substrate, and the semiconductor die includes chamfered edges. The conductive bumps are disposed between the semiconductor die and the organic interposer substrate, and the semiconductor die is electrically connected to the organic interposer substrate through the conductive bumps. The underfill is disposed between the semiconductor die and the organic interposer substrate, wherein the underfill encapsulates the conductive bumps and is in contact with the chamfered edges of the at least one semiconductor die. The insulating encapsulation covers the organic interposer substrate and laterally encapsulates the least one semiconductor die and the underfill.

Package structure

A package structure is provided. The package structure includes a semiconductor die bonding on a first surface of a redistribution structure through first bonding elements, and a wall structure bonding on the first surface of the redistribution structure through second bonding elements. The wall structure includes a plurality of partitions laterally arranged in a discontinuous ring, and the semiconductor die is located within the discontinuous ring. The package structure also includes a substrate on a second surface of the redistribution structure through third bonding elements and in electrical connection with the semiconductor die.

Package structure and method for forming the same

A system is provided. The system includes an exposing device configured to generate a real-time image, including multiple first align marks, of a mask and an adjusting device configured to adjust an off-set of the mask from a pre-determined position to be smaller than a minimum aligning distance according to the first align marks and multiple align marks on a substrate, and further to move the mask closer to the pre-determined position to have a displacement, less than a minimum mapping distance, from the pre-determined position according to the real-time image and a reference image of the mask.

Lithography system and method

A method of lithography process is provided. The method includes forming a conductive layer over a reticle. The method includes applying ionized particles to the reticle by a discharging device. The method includes forming a photoresist layer over a semiconductor substrate. The method includes securing the semiconductor substrate by a wafer electrostatic-clamp. The method also includes patterning the photoresist layer by emitting radiation from a radiation source via the reticle.

Method of lithography process and transferring a reticle

A particle removal method for removing particles on the backside of a reticle is provided. The method includes disposing the reticle on a reticle holder. In addition, the method includes moving a baffle defining an enclosed area that encompasses a particle to be removed on a backside of the reticle. The method further includes spraying, by a solution spraying module of a particle removal device, a solution onto the particle. The method further includes sucking, by a sucking module of the particle removal device, the solution on the reticle with the particle. The method further includes emitting, by the particle removal device, a gas onto the backside of the reticle for drying the backside.

Particle removal method

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package at least has a semiconductor die and a redistribution layer disposed on an active surface of the semiconductor die and electrically connected with the semiconductor die. The redistribution layer has a wiring-free zone arranged at a location below a corner of the semiconductor die. An underfill is disposed between the semiconductor die and the redistribution layer. The wiring-free zone is located below the underfill and is in contact with the underfill. The wiring-free zone extends horizontally from the semiconductor die to the underfill.

Semiconductor package and manufacturing method thereof

A reticle, a reticle container and a method of lithography process are provided. The reticle container includes: a cover configured to protect a reticle, a baseplate, and a discharging device on the baseplate. The baseplate has: a top surface configured to engage to the cover and a bottom surface opposite to the top surface. The discharging device is configured to neutralize static charges accumulated on the reticle.

Method of lithography process using reticle container with discharging device

A method includes forming a package component comprising forming a dielectric layer, patterning the dielectric layer to form an opening, and forming a redistribution line including a via in the opening, a conductive pad, and a bent trace. The via is vertically offset from the conductive pad. The conductive pad and the bent trace are over the dielectric layer. The bent trace connects the conductive pad to the via, and the bent trace includes a plurality of sections with lengthwise directions un-parallel to each other. A conductive bump is formed on the conductive pad.

Multi-bump connection to interconnect structure and manufacturing method thereof

A package structure is provided. The package structure includes a redistribution structure and a first semiconductor die over the redistribution structure. The package structure also includes a wall structure laterally surrounding the first semiconductor die and the wall structure includes a plurality of partitions separated from one another. The package structure also includes an underfill material between the wall structure and the first semiconductor die. The package structure also includes a molding compound encapsulating the wall structure and the underfill material.

Structures and formation methods of a chip package structure are provided. The chip package structure includes a semiconductor die bonded over an interposer substrate. The chip package structure also includes a warpage release layer structure. The warpage release layer structure includes an organic material layer and an overlying high coefficient of thermal expansion (CTE) material layer with a CTE that is substantially equal to or greater than 9 ppm/&#xb0; C. The organic material layer is in direct contact with the upper surface of the semiconductor die, and the overlying high CTE material layer covers the upper surface of the semiconductor die.

A system is disclosed. The system includes a cleaning device and a scanner device. The cleaning device is configured to clean a mask. The scanner device is coupled to the cleaning device and is configured to receive the mask, a reference image and a real-time image that is captured at the mask. The reference image includes at least one first mark image having a plurality of mapping marks on the mask. The real-time image includes at least one second mark image having the plurality of mapping marks on the mask. The scanner device is configured to map the at least one second mark image in the real-time image with the at least one first image in the reference image, when a lithography exposing process is performed. A method is also disclosed herein.

A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

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Jhudong, Taiwan

Tsung-Yen Lee