Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsung-Yao Wen

Sai-Hooi Yeong

Yen-Ming Chen

Sheng-Chen Wang

Sheng-chen Wang

Yee-Chia Yeo

Hung-Li Chiang

Cheng-Yi Peng

Jui-Yao Lai

Yao-De Chiou

Angus Hsiao

Hsueh-Chang Sung

Bo-Yu Lai

Ya-Yun Cheng

Ru-Gun Liu

Chih-Ming Lai

Chih-Liang Chen

Kam-Tou Sio

Chun-Kuang Chen

Hui-Ting Yang

Chew-Yuen Young

Mao-Nan Wang

A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.

Replacement gate process for FinFET

A fin field device structure and method for forming the same are provided. The FinFET device structure includes a protruding structure extending from a substrate and an anti-punch through implant (APT) region formed in the protruding structure. The FinFET device structure includes a barrier layer formed on the APT region, and the barrier layer has a width in a horizontal direction. The width gradually tapers from a bottom of the barrier layer to a top of the barrier layer.

Barrier layer above anti-punch through (APT) implant region to improve mobility of channel region of fin field effect transistor (finFET) device structure

A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate, forming a hard mask (HM) layer over the dielectric layer, forming a fin trench through the HM layer and the dielectric layer and extending down to the substrate, forming a semiconductor feature in the fin trench and removing the HM layer to expose an upper portion of the semiconductor feature to form fin features.

Method of semiconductor device fabrication

A method of forming a semiconductor device includes forming a fin protruding from a substrate, the fin having a channel region, a source/drain (S/D) region, and a biasing region, wherein the channel region and the biasing region sandwich the S/D region. The method further includes trimming the biasing region to reduce a height of the biasing region and forming a gate structure engaging the channel region. The method also includes forming a conductive feature electrically coupling to the biasing region.

FinFET transistor with fin back biasing

A semiconductor device includes a semiconductor substrate; a semiconductor projection connected to the semiconductor substrate; and a gate engaging the semiconductor projection, wherein the semiconductor projection includes a first region and a second region, the second region is between the first region and the gate, and the first region is lower in height than the second region.

A layout modification method is performed by at least one processor. The layout modification method includes: analyzing, by the at least one processor, allocation of a plurality of specific layout segments of a circuit cell layout to determine a first specific layout segment and a second specific layout segment from the plurality of specific layout segments; determining, by the at least one processor, if the first specific layout segment and the second specific layout segment are coupled to a first signal level; and merging, by the at least one processor, the first specific layout segment and the second specific layout segment into a first merged layout segment when the first specific layout segment and the second specific layout segment are coupled to the first signal level.

Layout modification method and system

A semiconductor device includes multiple first fins oriented lengthwise along a first direction and multiple first gate structures oriented lengthwise along a second direction generally perpendicular to the first direction. Each of the first fins includes an end that is narrower than a main body of the respective first fin. The first gate structures are disposed over channel regions of the main body of the first fins to form multiple first FinFETs. The end of the first fins and the channel regions of the first fins sandwich some of source/drain regions of the first fins. The semiconductor device further includes a first contact disposed over and in electrical contact with the ends of the first fins.

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a fin extending along a first direction over a substrate and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and a first insulating gate sidewall on a first lateral surface of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate structure. A portion of the source/drain region extends under the insulating gate sidewall for a substantially constant distance along the first direction.

Semiconductor device with epitaxial source/drain

A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an anti-punch through implant (APT) region formed in the fin structure and a barrier layer formed on the APT region. The barrier layer has a middle portion and a peripheral portion, and the middle portion is higher than the peripheral portion. The FinFET device structure further includes an epitaxial layer formed on the barrier layer.

Barrier layer above anti-punch through (APT) implant region to improve mobility of channel region of fin field effect transistor (FinFET) device structure

Structures and methods are provided for forming fin structures. A first fin structure is formed on a substrate. A shallow-trench-isolation structure is formed surrounding the first fin structure. At least part of the first fin structure is removed to form a cavity. A first material is formed on one or more side walls of the cavity. A second material is formed to fill the cavity, the second material being different from the first material. At least part of the STI structure is removed to form a second fin structure including the first material and the second material. At least part of the first material that surrounds the second material is removed to fabricate semiconductor devices.

Growing community of inventors

Hsinchu, Taiwan

Tsung-Yao Wen