Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Tsung-Shu Lin

Wei-Cheng Wu

Tsung-Yu Chen

Chen-Hua Douglas Yu

Hsien-Wei Chen

Wensen Hung

Der-Chyang Yeh

Chang-Chia Huang

Chi-Hsi Wu

Cheng-Hsien Hsieh

An-Jhih Su

Cheng-Chieh Hsieh

Li-Han Hsu

Chien-Chia Chiu

Hung-Chi Li

Chen-Shien Chen

Shih-Chang Ku

Meng-Tsan Lee

Chen-Hsiang Lao

Chen-Cheng Kuo

Hsien-Pin Hu

Wen-Hsin Wei

Ying-Ju Chen

Han-Ping Pu

Li-Hsien Huang

Chin-Chuan Chang

Ming-Da Cheng

Wei-Yu Chen

Yao-Chun Chuang

Chita Chuang

Sao-Ling Chiu

Chien-Yuan Huang

Bor-Rung Su

Chih-Kai Cheng

Shang-Yun Hou

Wen-Hsiung Lu

Ming-Yen Chiu

Ping-Kang Huang

Shih-Peng Tai

Shou-Yi Wang

Ping-Chang Wu

Shih-Hui Wang

Chin-Te Wang

Yi-Chung Huang

Hsuan-Ning Shih

Yuan Sheng Chiu

Tin-Hao Kuo

Yu-Feng Chen

Kuo-Chin Chang

Wen-Yi Lin

Yu-Chen Hsu

Wei-Chih Lai

Yuh Chern Shieh

Chien-Fu Tseng

Che-Yu Yeh

Yuan-Sheng Chiu

Shin-Puu Jeng

Hung-Jui Kuo

Po-Yao Lin

Jiun Yi Wu

Ming-Chih Yew

Yen-Liang Lin

Chun-Hung Lin

Hsin-Chieh Huang

Yi-Wen Wu

Wei-Ting Lin

Sheng-Yu Wu

Yu-Chih Liu

Ming Shih Yeh

Hao-Juin Liu

Ching-Fu Chang

Jing Ruei Lu

Yu-Ling Tsai

Hung-An Teng

Wei-yu Chen

Sheng-Han Tsai

Yao-Chun Chunag

Pei-Ti Yu

Chou-Jui Hsu

A method includes forming a plurality of dielectric layers over a semiconductor substrate, forming a plurality of metal lines and vias in the plurality of dielectric layers, forming a lower portion of an inner seal ring and a lower portion of an outer seal ring extending into the plurality of dielectric layers, depositing a first dielectric layer over the plurality of metal lines and vias, and etching the first dielectric layer to form an opening penetrating through the first dielectric layer. After the first dielectric layer is etched, a top surface of the lower portion of the inner seal ring is exposed, and an entire topmost surface of the lower portion of the outer seal ring is in contact with a bottom surface of the first dielectric layer. An upper portion of the inner seal ring is then formed to extend into the opening and to join the lower portion of the inner seal ring. A second dielectric layer is deposited to cover the upper portion of the inner seal ring.

Semiconductor package including step seal ring and methods forming same

A semiconductor package includes a first heat dissipation plate, a second heat dissipation plate, a plurality of heat generating assemblies, and a plurality of fixture components. The first heat dissipation plate has a first upper surface and a first lower surface. The first heat dissipation plate includes first through holes extended from the first upper surface to the first lower surface. The second heat dissipation plate has a second upper surface and a second lower surface. The second heat dissipation plate includes second through holes extended from the second upper surface to the second lower surface. The heat generating assemblies are disposed between the first heat dissipation plate and the second heat dissipation plate. The fixture components include fix screws and nuts. The fix screws penetrate through the first heat dissipation plate and the second heat dissipation plate along the first through holes and the second through holes.

Semiconductor package

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

Device and method for UBM/RDL routing

A manufacturing method of a semiconductor package includes the following steps. A package structure is provided over a substrate. A thermal interface layer is provided over the package structure. A lid structure is provided over the substrate, wherein the lid structure comprises a main body in contact with the package structure through the thermal interface layer and surrounding the package structure and a plurality of rib portions protruded from the main body and extended toward the package structure.

Method of manufacturing semiconductor package having lid structure

A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

Devices employing thermal and mechanical enhanced layers and methods of forming same

A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Semiconductor package and manufacturing method thereof

A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.

Stacked via structure disposed on a conductive pillar of a semiconductor die

A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

Semiconductor structure and manufacturing method thereof

A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a cap and outer flanges. The cap overlies the semiconductor package. The outer flanges are disposed at edges of the cap, are connected with the cap, and extend towards the circuit substrate. A region of the bottom surface of the cap has a curved profile matching a warpage profile of the semiconductor package and the circuit substrate, and the region having the curved profile extends over the semiconductor package.

Semiconductor device having heat dissipation structure of curved profile and a manufacturing method thereof

In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure.

Integrated circuit packages having mechanical brace standoffs

A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.

Package structure

An apparatus for manufacturing packaged semiconductor devices includes a lower plate having package platforms and clamp guide pins to align an upper plate with the lower plate, and a boat tray having windows configured to receive package devices, and a plurality of upper plates configured to be aligned to respective windows and respective package platforms. Clamping force can be applied by fasteners configured to generate a downward force upon the upper plate. Package devices on the platforms are thus subjected to a clamping force. Load cells measure the clamping force so adjustments can be made.

Package structure and method and equipment for forming the same

Semiconductor package comprising heat dissipation plates

A package structure includes a semiconductor device and an adhesive pattern. The adhesive pattern surrounds the semiconductor device, wherein an angle θ is formed between a sidewall of the semiconductor device and a sidewall of the adhesive pattern, 0°<θ<90° wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.

Growing community of inventors

Taipei, Taiwan

Tsung-Shu Lin