Taiwan Semiconductor Manufacturing Comp. Ltd.

Advanced Semiconductor Engineering, Inc.

Tsung-Hsun Lee

Po-Chung Cheng

Ching-Juinn Huang

Chi Ming Yang

Ming-Chiang Lee

Kuo-Hua Chen

Jian-Yuan Su

Chen-Chuan Fan

Li-Jui Chen

Kai-Fa Ho

Kai-Chieh Chang

In a method of pattern formation information including a pattern size on a reticle is received. A width of an EUV radiation beam is adjusted in accordance with the information. The EUV radiation beam is scanned on the reticle. A photo resist layer is exposed with a reflected EUV radiation beam from the reticle. An increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width is greater when the width before adjustment is W1 compared to an increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width when the width before adjustment is W2 when W1>W2.

Width adjustment of EUV radiation beam

In a method of pattern formation information including a pattern size on a reticle is received. A width of an EUV radiation beam is adjusted in accordance with the information. The EUV radiation beam is scanned on the reticle. A photo resist layer is exposed with a reflected EUV radiation beam from the reticle. An increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width is greater when the width before adjustment is Wcompared to an increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width when the width before adjustment is Wwhen W&#x3e;W

A lithography system is provided and includes a light source device configured to emit a processing light beam onto the semiconductor wafer, to generate a penetrating light beam and a reflected light beam. The lithography system further includes a detecting module having a first detector and a second detector. The first detector is configured to receive the penetrating light beam to generate first power data, and the second detector is configured to receive the reflected light beam to generate second power data. The lithography system also includes a monitoring device configured to calculate absorbed power data of the semiconductor wafer according to the first power data, the second power data and reference power data of a reference light beam and configured to compensate for a pattern formed on the semiconductor wafer resulting from the processing light beam according to the absorbed power data and reference information.

Lithography system and lithography method

A substrate structure is provided. The substrate structure includes a number of traces, a substrate core, a number of first metal tiles, a number of second metal tiles, a number of first electrically-functioning circuits, and a number of second electrically-functioning circuits. The substrate core has a first surface and a second surface opposite to the first surface. The traces, the first metal tiles, and the first electrically-functioning circuits are disposed on the first surface and add up to a first metal structure proportion, and the second metal tiles and the second electrically-functioning circuits are disposed on the second surface and add up to a second metal structure proportion. The difference between the first metal structure proportion and the second metal structure proportion is within 15%.

Substrate structure and package structure using the same

A system includes a wafer stage adapted to hold a semiconductor wafer thereon. A moveable temperature sensor array is configured to move to a plurality of different positions over a surface of the wafer stage and to take a plurality of temperature measurements at the plurality of positions, respectively. Based on the plurality of temperature measurements, a controller is adapted to determine an expected thermal deformation for the semiconductor wafer or for a reticle arranged over the semiconductor wafer.

Wafer or reticle thermal deformation measuring techniques

A substrate structure and a package structure using the same are provided. The substrate structure includes a number of traces, a substrate core and a number of first metal tiles. The substrate core has a first surface and a second surface opposite to the first surface. The first metal tiles are disposed on one of the first surface and the second surface, the minimum pitch between adjacent two of the first metal tiles is the minimum process pitch.

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Kaohsiung, Taiwan

Tsung-Hsun Lee