Nippon Telegraph and Telephone Corporation

Ntt Electronics Corporation

Tsuneo Mano

Junzo Yamada

Tsuneo Matsumura

Junichi Inoue

Shigeru Nakajima

Yukio Akazawa

Nobutaro Shibata

Hiroshi Inokawa

Tetsushi Sakai

Masayuki Ino

Nobuaki Ieda

This invention provides a semiconductor device including a silicon layer, an insulating layer formed on the silicon layer, a first semiconductor device formed on the insulating film to convert light into an electric signal, and a second semiconductor device formed on the insulating film, wherein a silicon region is formed in the silicon layer to shield the second semiconductor device from light, and a through hole extending through the silicon layer except for the silicon region to input light to the first semiconductor device is formed in that portion of the silicon layer corresponding to the lower portions of the first and second semiconductor devices.

Semiconductor device

A semiconductor memory includes a plurality of memory cells which are arranged in a matrix and respectively store data, a plurality of bit lines and a plurality of word lines, connected to the plurality of memory cells, for performing read/write access of data to the memory cells, and a test circuit. In the test circuit, an external terminal sends test data and expected value data written in the memory cells. A simultaneous write circuit simultaneously writes the test data from the external terminal in the plurality of memory cells connected to a selected word line. A simultaneous comparison circuit simultaneously compares the test data written in the plurality of memory cells connected to the selected word line with the expected value data supplied from the external terminal in correspondence with the selected word line.

Semiconductor memory having test circuit and test method thereof

A memory device which employs multilevel memory cells has a basic arrangement in which a write device writes multilevel information corresponding to binary data of plural bits in the memory cells and a readout device outputs binary data of plural bits representing the multilevel information read out of the memory cells. The memory device includes a multilevel detector for detecting the information of the memory cells at one time and reference level generator for generating reference levels therefor, thereby permitting the reduction of the bit area of each memory cell and increased speed during the operation of the memory device.

Memory device employing multilevel storage circuits

In a semiconductor memory, a memory cell array is divided into a plurality of sub arrays in a direction perpendicular to word lines. In each sub array sub word lines and bit lines are disposed to intersect each other and memory cells are disposed at all their intersections. Two different sub arrays constitute a unit cell array. The sub word line connected to a cell transistor in one of or the first the sub arrays of the unit cell array is connected to a first main word line and a second main word line which is not connected to the cell transistor in the first sub array is passed therethrough for connection with the sub word line of the other or second sub array in the unit cell array.

Semiconductor memory

Growing community of inventors

Ebina, Japan

Tsuneo Mano