Sumitomo Electric Industries, Limited

Toyota Jidosha Kabushiki Kaisha

Denso Corporation

Rohm Co., Ltd.

Kyoto University

Other

Tokyo Electron Limited

Brillar Co., Ltd.

Tsunenobu Kimoto

Hiroyuki Matsunami

Shin Harada

Kenichi Hirotsu

Kazuhiro Fujikawa

Satoshi Hatsukawa

Takashi Hoshino

Masatoshi Aketa

Nobuhiko Fujita

Tadashi Tomikawa

Yuuichi Takeuchi

Yuki Nakano

Hiromu Shiomi

Akinori Seki

Mitsuhiro Kataoka

Masami Naito

Katsunori Danno

Rajesh Kumar

Takuma Kobayashi

Hiroaki Saitoh

Jun Yoshikawa

Rajesh Kumar Malhan

Noriaki Kawamoto

Ikuo Sawada

Eisuke Morisaki

Hirokatsu Kobayashi

Iso Ohara

Keita Tachiki

Shin c/o Osaka Works Of Sumitomo Electric Harada

Kenichi c/o Osaka Works Of Sumitomo Hirotsu

Shin Osaka Works Sumitomo Elec Ind Ltd Harada

Kenichi Osaka Works Sumitomo Elec Ind Hirotsu

A SiC semiconductor device manufacturing method includes a step of etching a surface of a SiC substratewith Hgas at a temperature of 1200° C. or more, a step of forming a SiOfilmon the SiC substrate under conditions where the SiC substrate is not oxidized, and a step of thermally treating the SiC substrate formed with the SiOfilm in Ngas atmosphere at a temperature of 1350° C. or more.

SiC semiconductor device manufacturing method and SiC semiconductor device

A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×10cmor more, a SiOlayer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiOlayer and in which a carbon density gradually decreases toward the non-connection surface of the SiOlayer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiOlayer and that has a carbon density of 1.0×10cmor less.

Semiconductor device with carbon-density-decreasing region

The method for manufacturing a crystal for a synthetic gem includes the step of preparing a SiC single crystal including an n-type impurity, and the step of irradiating the SiC single crystal with an electron beam to generate a carbon vacancy in the SiC single crystal. Irradiation energy and dose in electron beam irradiation are set such that the density of the carbon vacancy is higher than the density of the n-type impurity.

Method for manufacturing crystal for synthetic gem

A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0&#xd7;10cmor more, a SiOlayer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiOlayer and in which a carbon density gradually decreases toward the non-connection surface of the SiOlayer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiOlayer and that has a carbon density of 1.0&#xd7;10cmor less.

A process for producing a semiconductor device includes: forming an SiC epitaxial layer on an SiC substrate; implanting the epitaxial layer with ions; forming a gettering layer having a higher defect density than a defect density of the SiC substrate; and carrying out a heat treatment on the epitaxial layer. The semiconductor device includes an SiC substrate, an SiC epitaxial layer formed on the SiC substrate, and a gettering layer having a higher defect density than a defect density of the SiC substrate.

Gettering process for producing semiconductor device

A method of production of an SiC semiconductor device, which can form an ohmic electrode while preventing electrode metal from diffusing in the SiC single crystal substrate, includes a step of forming an ohmic electrode on an SiC substrate, characterized by forming a gettering layer with a defect density higher than the SiC substrate on that substrate to be parallel with the substrate surface, then forming the ohmic electrode the gettering layer outward from the substrate.

Method of production of SiC semiconductor device

A disclosed film deposition apparatus includes a process chamber inside which a reduced pressure space is maintained; a gas supplying portion that supplies a film deposition gas to the process chamber; a substrate holding portion that is made of a material including carbon as a primary constituent and holds a substrate in the process chamber; a coil that is arranged outside the process chamber and inductively heats the substrate holding portion; and a thermal insulation member that covers the substrate holding portion and is arranged to be separated from the process chamber, wherein the reduced pressure space is separated into a film deposition gas supplying space to which the film deposition gas is supplied and a thermal insulation space defined between the substrate holding portion and the process chamber, and wherein a cooling medium is supplied to the thermal insulation space.

Film deposition apparatus and film deposition method

A p-type SiC semiconductor includes a SiC crystal that contains Al and Ti as impurities, wherein the atom number concentration of Ti is equal to or less than the atom number concentration of Al. It is preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)&#x2267;5&#xd7;10/cm; and 0.01%&#x2266;(Concentration of Ti)/(Concentration of Al)&#x2266;20%. It is more preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)&#x2267;5&#xd7;10/cm; and 1&#xd7;10/cm&#x2266;(Concentration of Ti)&#x2266;1&#xd7;10/cm.

P-type SiC semiconductor

A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is &#x3c;11-20&#x3e;. A trench is formed on the SiC to have a stripe structure extending toward a &#x3c;11-20&#x3e; direction. An SiC epitaxial layer is formed on an inside surface of the trench.

Silicon carbide semiconductor device

A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

Lateral junction field effect transistor and method of manufacturing the same

A lateral JFET has a basic structure including an n-type semiconductor layer () formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (). Moreover, in the p-type semiconductor layer, there are provided a p-type gate region layer () extending into the n-type semiconductor layer () and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer () and an n-type drain region layer () spaced from the p-type gate region layer () by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.

Lateral junction field-effect transistor

On an SiC single crystal substrate, an electric field relaxation layer and a p&#x2212; type buffer layer are formed. The electric field relaxation layer is formed between the p&#x2212; type buffer layer and the SiC single crystal substrate to contact SiC single crystal substrate. On the p&#x2212; type buffer layer, an n type semiconductor layer is formed. On the n type semiconductor layer, a p type semiconductor layer is formed. In the p type semiconductor layer, an n+ type source region layer and an n+ type drain region layer are formed separated by a prescribed distance from each other. At a part of the region of p type semiconductor layer between the n+ type source region layer and the n+ type drain region layer, a p+ type gate region layer is formed.

Field effect transistor

A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600&#xb0; C.

Method for manufacturing semiconductor device having trench in silicon carbide semiconductor substrate

Growing community of inventors

Kyoto, Japan

Tsunenobu Kimoto