Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Tsunehiro Ino

Yuuichi Kamimuta

Akira Takashima

Yasushi Nakasaki

Masato Koyama

Akira Nishiyama

Daisuke Matsushita

Shosuke Fujii

Masamichi Suzuki

Koichi Muraoka

Masao Shingu

Yusuke Higashi

Naoki Yasuda

Jun Fujiki

Masahiro Koike

Kazuhiko Yamamoto

Nobutoshi Aoki

Akio Kaneko

Toshinori Numata

Shoko Kikuchi

Yukihiro Nomura

Ayaka Suko

Koichi Kato

Kenichiro Toratani

Takamitsu Ishihara

Misako Morota

Kouichi Muraoka

Keiko Ariyoshi

Reika Tanaka

Riichiro Takaishi

Shigeyuki Hirayama

Koji Usuda

Takayuki Sasaki

Seiji Inumiya

A storage device includes a first electrode, a second electrode, and a resistance change storage layer between the first and second electrodes. The storage layer is either in a first resistance state or in a second resistance state having a resistance higher than the first resistance state and contains at least two elements selected from a group consisting of germanium, antimony, and tellurium. The storage device further includes an interface layer between the first electrode and the resistance change storage layer. The interface layer contains at least one of the elements of the resistance change storage layer and includes a conductive region and an insulating region.

Storage device

A semiconductor device manufacturing method of embodiments includes: forming an aluminum nitride film; forming an aluminum hydroxide film containing diaspore-type aluminum hydroxide by performing treatment in a fluid containing water to the aluminum nitride film; and forming an aluminum oxide film containing α-type aluminum oxide by performing heat treatment to the aluminum hydroxide film at a temperature equal to or more than 500° C. and equal to or less than 800° C.

Semiconductor device manufacturing method, semiconductor memory device manufacturing method, semiconductor memory device, and substrate treatment apparatus

A memory device according to an embodiment includes a semiconductor layer, a gate electrode layer, and a first dielectric layer provided between the semiconductor layer and the gate electrode layer. The first dielectric layer contains aluminum (Al), a first element, nitrogen (N), and silicon (Si). The first element is at least one element selected from the group consisting of scandium (Sc), yttrium (Y), lanthanoid (Ln), boron (B), gallium (Ga), and indium (In).

Memory device with ferroelectric layer

A memory device including a first conductive layer; a second conductive layer; a resistance change region provided between the first conductive layer and the second conductive layer; a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium, vanadium, tantalum, and titanium, and a second element selected from the group consisting of oxygen, sulfur, selenium, and tellurium, the first region having a first atomic ratio of the first element to the second element; and a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.

Memory device with a plurality of metal chalcogenide layers

A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.

Ferroelectric memory device

A semiconductor memory device of an embodiment includes: a semiconductor layer; a gate electrode layer; a first insulating layer provided between the semiconductor layer and the gate electrode layer; a second insulating layer provided between the first insulating layer and the gate electrode layer; and an intermediate layer provided between the first insulating layer and the second insulating layer, the intermediate layer containing a first crystal of a space group Pbca (space group number), a space group P4/nmc (space group number), or a space group R-m (space group number), and the intermediate layer containing hafnium (Hf), oxygen (O), and nitrogen (N).

Semiconductor memory device

A semiconductor memory device includes: a first and a second electrodes aligned in a first direction; a first semiconductor layer provided between the first and the second electrodes; a second semiconductor layer provided between the first semiconductor layer and the second electrode; a first charge accumulating layer provided between the first electrode and the first semiconductor layer; and a second charge accumulating layer provided between the second electrode and the second semiconductor layer. At least one of the first and the second charge accumulating layers include: a first and a second regions including nitrogen, aluminum, and oxygen and having different positions in a second direction; and a third region provided between the first and the second regions in the second direction. Oxygen is not included in the third region or a concentration of oxygen in the third region is lower than that in the first and the second regions.

Semiconductor memory device having a charge accumulating layer including aluminum, oxygen, and nitrogen

According to an embodiment, a memory device includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting with the first direction, an insulating layer provided between the first conductive layer and the second conductive layer, and a dielectric layer provided between the first conductive layer and the third conductive layer, and between the insulating layer and the third conductive layer, the dielectric layer having a first thickness thinner than a second thickness, the first thickness being a thickness between the first conductive layer and the third conductive layer, the second thickness being a thickness between the insulating layer and the third conductive layer, and the dielectric layer including an oxide including at least one of hafnium oxide and zirconium oxide.

A memory device according to an embodiment includes a first conductive layer, a second conductive layer, and a first layer provided between the first conductive layer and the second conductive layer and containing aluminum oxide that contains at least one first element selected from the group consisting of magnesium (Mg), silicon (Si), hafnium (Hf), tungsten (W), and ruthenium (Ru), and the aluminum oxide is a ferroelectric.

Memory device

A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.

According to one embodiment, a semiconductor memory device includes a first conductive member, a first semiconductor member, and a first stacked member provided between the first conductive member and the first semiconductor member. The first stacked member includes a first insulating film, a second insulating film provided between the first insulating film and the first semiconductor member, first and second layers. The first layer includes aluminum and nitrogen and is provided between the first and second insulating films. A first thickness of the first layer along a first direction is 3 nm or less. The first direction is from the first semiconductor member toward the first conductive member. The second layer contacts the first layer, includes silicon and nitrogen, and is provided at one of a position between the first layer and the second insulating film or a position between the first layer and the first insulating film.

Semiconductor memory device and method for manufacturing the same with increased storage capacity

A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric film or a ferrielectric film provided between the first conductive layer and the second conductive layer, the ferroelectric film or the ferrielectric film including hafnium oxide containing at least one first element selected from Zn, Mg, Mn, Nb, Sc, Fe, Cr, Co, In, Li and N.

Semiconductor device and dielectric film

A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric layer including hafnium oxide provided between the first conductive layer and the second conductive layer, a sum of hafnium (Hf) and oxygen (O) in the hafnium oxide being 98 atomic percent or more.

Growing community of inventors

Fujisawa, Japan

Tsunehiro Ino