Hitachi, Ltd.

Tsuguo Matsuura

Tsuguo Shimizu

Shunichi Torii

Tadaaki Isobe

Naonobu Sukegawa

Toshimitsu Ando

Masanao Ito

Toshihiko Odaka

Tetsuhito Nakamura

A memory system having a DRAM or synchronous DRAM as a memory unit. A memory controller which controls the memory unit in correspondence with a memory access request received from a memory access request generator, has a row address buffer for storing a row address extracted from an issued memory access request, avoiding registration of same row address into different positions, a pointer register for storing a pointer to a registration entry in the row address buffer holding the row address, correspondence detection circuit that detects whether or not row addresses of issued access requests correspond with each other by comparing stored pointers, and a memory unit control circuit which continuously issues column addresses of plural requests with row addresses corresponding with each other to the DRAM.

Memory system

A memory control unit connected to a scalar processor having a buffer for storing a copy of block data of a main storage and a vector processor having a store requester for writing data into the main storage is disclosed. The memory control unit has a block valid memory having a one-bit valid bit for all blocks. The valid bit represents that the copy of the block data corresponding to said bit is in the buffer of the scalar processor. The memory control unit further has a block group valid table which has a block group bit for each block group. The block group bit represents whether any one of the block valid bits of the block belonging to the corresponding group is valid or not. When the vector processor stores the data into the main storage by the store requester, the memory control unit first searches the block group valid table to check whether the block group valid bit of the block group including the store address is valid or not. If it is valid, the memory control unit further searches the block valid memory to check whether the block valid bit of the block including the store address is valid or not. If it is valid, it invalidates the buffer of the scalar processor.

Memory control device with vector processors and a scalar processor

A vector processor for executing vector instructions comprises a plurality of vector registers and a plurality of pipeline arithmetic logic units. The vector registers are constructed with a circuit which operates in a speed equal to 2n times as fast as the processing speed of the pipeline arithmetic logic units. Either the read or the write operation from or to the vector registers are carried out in the time obtained by a processing cycle of each of the pipeline arithmetic logic units multiplied by n/2.

Vector processor

A multiprocessor system includes a plurality of central processing units (CPUs), which have a main storage in common, and a key storage for storing therein control information for storage protection of, reference to, and change in the main storage. Each CPU is provided with the key storage, the CPUs are connected by interface lines so as to form a ring-like combination, a CPU in which a key access request is generated, carries out the key processing for its own key storage and supplies the interface line with an address, data and others which are contained in the key access request, and another CPU receives the address, data and others to perform the key processing for its own key storage. A signal for determining the priority among key access requests simultaneously generated in a plurality of central processing units circulates through the CPUs via the interface lines, one of the CPUs having generated the key access requests catches the priority determining signal to make its own key access request valid, and prevents the circulation of the priority determining signal for a time till the key processing based upon the valid request has been completed.

Data processing system having ring-like connected multiprocessors

This data processing system includes a main memory which is shared by a plurality of central processor units (CPUs) which are also coupled in cascade in a closed circular path. Each CPU has a cache buffer memory and two sets of transfer registers for receiving and transmitting cancel request signals which identify cache data which is no longer valid. Each CPU's receiving register subsystem includes circuitry for invalidating cache buffer data which has been updated or rewritten in main memory by another CPU in the loop. Each CPU's transmitting register subsystem includes circuitry for inhibiting the transmittal of a cancel request signal if the next CPU in the circle is the same one which originated the particular cache invalidation signal. Circuitry is also provided for propagating a cancel request signal around the loop in opposite directions simultaneously.

Multiprocessor system with apparatus for propagating cache buffer

A multiprogrammed data processing system with reduced processing time for interlock instructions compares the first partial address contained in a request with a corresponding first partial address of an interlocked address in a first comparator when a main storage control unit receives the request from one of central processing units. The main storage control unit sends the request to a main memory in response to non-coincidence signal from the first comparator. In response to a coincidence signal from the first comparator, the main storage control unit compares a second partial address contained in the request with a corresponding second partial address of the interlocked address. The main storage control unit sends the request in response to a non-coincidence signal from the second comparator.

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Hadano, Japan

Tsuguo Matsuura