Arcadia Design Systems, Inc.

Hitachi Micro Systems, Inc.

Apex Design Systems, Inc.

Tsu-Wei Ku

Wei-Kong Chia

Duan-Ping Chen

Hau-Yung Chen

Scot A Woodward

Yulin Chen

Rwei-Cheng Lo

Yung-Hung Wang

Wen-Chung Fang

Dong-Ru Shieh

An EDA (Electronic Design Automation) process which collects and moves empty-spaces among cells on a circuit layout to one or more target areas for productive use, such as chip-size reduction and routability congestion alleviation. The process includes globally moving the empty-spaces to the target area and thereafter locally moving the empty-spaces as refinement.

Chip-area reduction and congestion alleviation by timing-and-routability-driven empty-space propagation

The invention discloses a relative structure placement of datapath of cell instances in a column structure, a row structure, or an array structure. To encourage placement of a desirable structure, pseudo cells, pseudo pins, and pseudo nets are selected to be placed at certain locations with respect to real cell instances. The end result produces a cluster of real cell instances that form a desirable structure while minimizing the length of nets. The invention further discloses a non-uniform partitioning of a density map for calculating a force update vector. The partitioning is taken over a region A to compute Riemann sum approximations of a function F over the region A. A force update vector is calculated for a given cell instance within the region A where neighboring cell instances have an exponentially larger grid size as cell instances extend further away from the given cell instance.

Method and apparatus of relative datapath cell placement with structure bonding

The invention resides in a computer-aided design system for defining physical placement and floor-planning of electronic circuits on a given substrate. Improve utilization of substrate area is achieved by arranging circuits into structural (e.g., data-path) and non-structural (e.g., non-data-path) zones for effectively segregated chip or board lay-out. Software is provided to receive a netlist file and determine therefrom which components are categorizable within structural portion. Furthermore, software is provided to produce a lay-out file which defines physical placement of the prototype design, wherein structural components are inter-placed with related control components, for example, to provide sliced-structure placement of a semiconductor chip.

Method for mixed placement of structured and non-structured circuit

A logic simulation system and method reduces the number of events to be simulated. The simulator receives a user specified circuit netlist denoting a specified logic circuit's components and the nodes interconnecting those components. A user specified watched nodes list identifies the circuit nodes for which output waveforms are to be generated. A cell library provides cell delay data representing signal delays from each input port to each output port of each circuit component. A set of input signal waveforms are compiled into a sequence of variable length time periods and each input signal is assigned an extended boolean value for each time period. The extended boolean values identify signals that are stable over the time period, signals with a single transition during the time period, and signals with multiple transitions during the time period. For each time period, operation of the logic circuit is initially simulated without determining when signal transitions on the circuit's nodes occur, by performing an extended zero delay simulation. The extended zero delay simulation assigns to each circuit node an extended boolean signal value selected from the set consisting of stable signal values (0, 1, X and Z), signal values (t0, t1, tX, tZ) having a single transition during the time period, and a signal value (mt) indicating more than one transition during the time period. For each time period, the circuit is backtracked from those watched nodes assigned non-stable values so as to identify nodes that control those watched nodes and that were assigned non-stable values. Then event driven simulation of the logic circuit is performed for events on those identified nodes.

Logic circuit simulator and logic simulation method having reduced

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Cupertino, CA, United States of America

Tsu-Wei Ku