Aptos Corporation

Tsing-Chow Wang

Te-Sung Wu

Chung W Ho

Kuolung Lei

Erh-Kong Chieh

Tony Shen

Susana Samoranos

Nguyen Khe

A method of making an electrical contact bump electrical contact structure on a substrate comprising: providing a substrate having a bond pad, and a passivation layer overlying a portion for the substrate and wherein the passivation layer includes an opening therein exposing a portion of the bond pad, and wherein the passivation layer has a raised portion overlying the bond pad; forming an under bump metallurgy over at least the exposed portion of the bond pad and over at least a portion of the raised portion of the passivation layer overlying the bond pad; forming a sacrificial blanket having an opening therein that in cross-section has an inverted T-shape over the substrate so that the opening in the sacrificial blanket is aligned with the bond pad; and depositing an electrically conductive material into the opening in the sacrificial blanket.

Flat-top bumping structure and preparation method

A semiconductor die package design incorporating at least a pair of functional semiconductor dies. The input/output pads locations on one of the dies (the daughter die) are located at the near mirror image of the original die (mother die). The package architecture includes two dies back-to-back or stacked dies back-to-back, therefore a plurality of input/output interconnections can be formed. The package increases density and performance by twofold or more compared to a regular package containing only one die with the same footprint. At least one additional pin can be dedicated as the chip select pin for the daughter die or multiple dies. The other pins can be shared with the mother die.

Stacked paired die package and method of making the same

Within a method for forming a patterned polyimide layer, there is first provided a substrate. There is then formed over the substrate a blanket polyamic acid layer. There is then formed upon the blanket polyamic acid layer a patterned photoresist layer. There is then hardened the patterned photoresist layer to form a hardened patterned photoresist layer. There is then patterned, while employing the hardened patterned photoresist layer as an etch mask layer, the blanket polyamic acid layer to form a patterned polyamic acid layer. Finally, there is then thermally annealed the patterned polyamic acid layer to form a patterned polyimide layer. By employing as an etch mask when forming from the blanket polyamic acid layers the patterned polyamic acid layer the hardened patterned photoresist layer, rather than an unhardened patterned photoresist layer, the patterned polyamic acid layer, and consequently also the patterned polyimide layer, are formed with enhanced dimensional control.

Method for forming patterned polyimide layer

Within both a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is first provided a substrate. Within the method, there is then formed over the substrate a patterned bond pad layer. There is then formed over the patterned bond pad layer a barrier layer comprising: (1) a first titanium-tungsten alloy layer; (2) a titanium-tungsten alloy nitride layer formed upon the first titanium-tungsten alloy layer; and (3) a second titanium-tungsten alloy layer formed upon the titanium-tungsten alloy nitride layer. Finally, there is then formed upon the barrier layer a seed layer which comprises a titanium layer formed upon the barrier layer. The method contemplates a microelectronic fabrication fabricated employing the method. The barrier layer provides enhanced barrier properties within the microelectronic fabrication within which is formed the barrier layer.

Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties

Within a method for fabricating a microelectronic fabrication, and a microelectronic fabrication fabricated employing the method, there is first provided a substrate. Within the method, there is then formed over the substrate a patterned bond pad layer. There is also formed over the substrate a patterned passivation layer which passivates a series of edges of the patterned bond pad layer while leaving exposed a central portion of the patterned bond pad layer, where the patterned passivation layer has a series of protrusions within the patterned passivation layer over the series of edges of the patterned bond pad layer. There is then formed over the central portion of the patterned bond pad layer and bridging over the series of protrusions of the patterned passivation layer a first terminal electrode layer having an upper surface which is concave. Finally, there is then formed over the first terminal electrode layer a second terminal electrode layer having an upper surface which is other than concave. The method otherwise contemplates the microelectronic fabrication fabricated employing the method. A terminal electrode structure which comprises the first terminal electrode layer and the second terminal electrode layer provides enhanced passivation of the microelectronic fabrication and enhanced bondability to the terminal electrode structure.

Microelectronic fabrication having formed therein terminal electrode structure providing enhanced passivation and enhanced bondability

Within a method for forming a solder interconnection structure for use within a microelectronic fabrication, there is first provided a substrate having formed thereover a bond pad. There is then formed upon the bond pad a first solder interconnection layer. There is then formed over the first solder interconnection layer an annular solder non-wettable copper oxide layer which does not cover an upper dome portion of the first solder interconnection layer. There is then formed over the upper dome portion of the first solder interconnection layer and not upon the annular solder non-wettable copper oxide layer a second solder interconnection layer.

Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball

Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a patterned bond pad layer. There is also formed over the substrate and in electrical communication with the patterned bond pad layer a patterned redistribution layer, wherein the patterned redistribution layer is formed employing a plating method. The method is particularly economical for fabricating the microelectronic fabrication.

Method for fabricating a microelectronic fabrication having formed therein a redistribution structure

Within both a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing, the method, there is first provided a substrate. Within the method, there is then formed over the substrate a patterned bond pad layer. There is then formed over the patterned bond pad layer a barrier layer comprising: (1) a first titanium-tungsten alloy layer; (2) a titanium-tungsten alloy nitride layer formed upon the first titanium-tungsten alloy layer; and (3) a second titanium-tungsten alloy layer formed upon the titanium-tungsten alloy nitride layer. Finally, there is then formed upon the barrier layer a seed layer which comprises a titanium layer formed upon the barrier layer. The method contemplates a microelectronic fabrication fabricated employing the method. The barrier layer provides enhanced barrier properties within the microelectronic fabrication within which is formed the barrier layer.

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Cupertino, CA, United States of America

Tsing-Chow Wang