Winbond Electronics Corporation

National Yang Ming Chiao Tung University

U.S. Philips Corporation

National Science Council

Tseung-Yuen Tseng

Pang Lin

Chao-Cheng Lin

Chih-Yi Liu

Chun-Chieh Lin

Chun-Chieh Chuang

Fa-Shen Jiang

Dai-Ying Lee

Wen-Hsi Lee

Chu-Jie Huang

Chih-Chieh Yang

Chia-Ying Lee

Seu-Yi Li

Sheng-Yu Wang

Chun-An Lin

Pei-Hsun Wu

Guang-Jyun Dai

Shean Yiah Lee

Ming Shiahn Tsai

Huei-Mei Tsai

Tsung-Ling Tsai

Zhien C Chen

Chung-Jung Hung

Chen-Han Tsai

Provided is a composite electrode material. The composite electrode material is disposed on a surface of an electrode. The composite electrode material includes a plurality of conductive material layers and a plurality of active material layers. The conductive material layers and the active material layers are alternately stacked along a direction non-parallel to the surface of the electrode, and are arranged disorderly along a direction parallel to the surface of the electrode.

Composite electrode material

A conductive-bridging random access memory and a method for fabricating a conductive-bridging random access memory are provided. The conductive-bridging random access memory includes a bottom electrode layer on a semiconductor substrate, an electrical resistance switching layer on the bottom electrode layer, an electron-capturing layer on the electrical resistance switching layer, a barrier layer on the electron-capturing layer, an ion source layer on the barrier layer, and a top electrode layer on the ion source layer. The electron-capturing layer includes electron-capturing material, and the electron affinity of the electron-capturing material is at least 60 KJ/mole.

Conductive-bridging random access memory and method for fabricating the same

A conductive-bridging random access memory is provided. The conductive-bridging random access memory includes a bottom electrode layer on a semiconductor substrate, an electrical resistance switching layer on the bottom electrode layer, a barrier layer on the electrical resistance switching layer, a top electrode layer on the barrier layer, and a high thermal-conductive material layer between the bottom electrode layer and the barrier layer. The high thermal-conductive material layer has a thermal conductivity in a range of 70-5000 W/mK.

Conductive-bridging random access memory

A high energy density asymmetric pseudocapacitor includes a cathode plate, an anode plate, and a separator. The cathode plate includes a first conductive substrate and a porous cathode film formed on the first conductive substrate. The porous cathode film includes a carbon nano-tube network and a plurality of composite flakes. Each of the composite flakes contains graphene, a transition metal compound and carbon nano-tubes. The anode plate includes a second conductive substrate and an anode film formed on the second conductive substrate. The anode film contains graphene and carbon nano-tubes.

High energy density asymmetric pseudocapacitor and method of making the same

An exemplary embodiment of a non-volatile memory includes a bottom conductive layer, a resistive switching layer, an oxygen vacancy barrier layer and an upper conductive layer. The resistive switching layer is disposed on the bottom conductive layer. The oxygen vacancy barrier layer is disposed on the resistive switching layer. The upper conductive layer is disposed on the oxygen vacancy barrier layer.

Non-volatile memory with oxygen vacancy barrier layer

A method for fabricating a resistor for a resistance random access memory (RRAM) includes: (a) forming a first electrode over a substrate; (b) forming a variable resistance layer of zirconium oxide on the first electrode under a working temperature, which ranges from 175&#xb0; C. to 225&#xb0; C.; and (c) forming a second electrode of Ti on the variable resistance layer.

Method for fabricating a resistor for a resistance random access memory

Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiOfilm is disposed over the metal layer. A resistor layer comprising a SrZrOfilm is disposed on the buffer layer. A top electrode is disposed on the resistor layer.

Nonvolatile memory and fabrication method thereof

This invention relates to a process for fabricating ZnO nanowires with high aspect ratio at low temperature, which is associated with semiconductor manufacturing process and a gate controlled field emission triode is obtained. The process comprises providing a semiconductor substrate, depositing a dielectric layer and a conducting layer, respectively, on the semiconductor substrate, defining the positions of emitter arrays on the dielectric layer and conducting layer, depositing an ultra thin ZnO film as a seeding layer on the substrate, growing the ZnO nanowires as the emitter arrays by using hydrothermal process, and etching the areas excluding the emitter arrays, then obtaining the gate controlled field emission triode.

Gate controlled field emission triode and process for fabricating the same

A method for non-volatile memory fabrication is provided, in which a substrate is provided, a bottom electrode is formed on the substrate, a solution with precursors of Zr and Sr is coated on the bottom electrode, the solution on the bottom electrode surface is dried and then fired to form a resistor layer of SrZrO, and a top electrode is formed on the resistor layer.

Method for non-volatile memory fabrication

A nonvolatile memory and a fabrication method thereof. The nonvolatile memory includes a substrate, a bottom electrode deposited on the substrate, a resistor layer deposited on the bottom electrode, and a top electrode on the resistor layer. The bottom electrode includes LaNiOand the resistor layer includes doped SrZrO.

A ferroelectric memory structure is disclosed. The ferroelectric memory structure includes a substrate, an insulating layer formed on the substrate, a plurality of oxide electrodes formed on the insulating layer, a ferroelectric layer formed on the insulating layer and the plurality of oxide electrodes, and a plurality of metallic electrodes formed on the ferroelectric layer and corresponding to the plurality of the oxide electrodes.

Ferroelectric memory structure and fabrication method thereof

A novel SBTN (Sr Bi Ta Nb O ) thin film which exhibits satisfactory ferroelectric properties is disclosed, wherein a lies between 0.5 and 1, b lies between 2 and 2.7, c lies between 1 and 1.4, d lies between 0.6 and 1.1, and x lies between 8 and 10. The composition of Sr Bi Ta Nb O wherein x lies between 9 and 10 is preferred. The Sr Bi Ta Nb O thin film is formed by two-target off-axis RF magnetron sputtering at a temperature down to about 600&deg; C. One target is formed of Sr Bi Ta Nb O , and the other target is formed of Bi O .

SBTN ferroelectric thin film and method for producing same

A ceramic composition on the basis of a doped BaTiO.sub.3, a ceramic multilayer having such ceramic composition and a monolithic capacitor having such a composition are provided according to the invention. The composition corresponds to the formula

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Hsinchu, Taiwan

Tseung-Yuen Tseng