Nan Ya Technology Corporation

Tse Yao Huang

Yinan Chen

Shih-Chi Hsu

Tzu-Ching Tsai

Jengping Lin

Lin-Chin Su

Hsing-Chuan Tsai

Yun Sen Lai

Shih-chi Hsu

A method for fabricating a self-aligned contact hole in accordance with the present invention is disclosed. First a conductive layer, a silicon oxide layer, and a first silicon nitride layer are formed on a silicon substrate. Next, the first silicon nitride layer, the silicon oxide layer, and the conductive layer are etched to form a trench. Then, a BPSG layer is formed over the first silicon nitride layer. A photoresist layer having an opening is defined. Then, using the photoresist layer as the masking layer, a part of BPSG layer is etched to form a self-aligned hole. Next, the photoresist layer is removed. Afterward, a second silicon nitride layer is formed and etched back to form a spacer.

Method for fabricating self-aligned contact hole

This present discloses a method for STI top rounding control, the steps comprising: (a) providing a semiconductor substrate; (b) forming an oxide layer on the substrate; (c) forming a hard mask on the oxide layer; (d) forming a photoresist pattern with an opening exposing the hard mask at a predetermined STI trench region on the hard mask; (e) etching the exposed hard mask and the underlying oxide layer within the opening in sequence, and continuously over-etching to remove part of the semiconductor substrate to form a window lower than the surface of the oxide layer; and (f) using the photoresist pattern and the hard mask as an etching mask, removing part of the exposed semiconductor substrate in the window to form an STI trench.

Method for STI-top rounding control

This present invention provides methods for isolating interconnects characterized by first isolating the top and bottom interconnects with an IMD consisting of a traditional low-k dielectric material, then dissolving the low-k material with a suitable solvent and using air or a noble gas instead of the traditional low-k dielectric material to isolate the interconnects.

Methods for isolating interconnects

The present invention discloses a method of forming a crown capacitor for a DRAM cell. An etching method having different selectivity between the BPSG and silicon oxynitride layer is applied to form a sacrificial structure with a concanovenex sidewall. Using the sacrificial structure as a mold, a high capacitance crown capacitor is obtained.

Method of forming a crown capacitor for a DRAM cell

A method for fabricating a DRAM capacitor is described. First, a semiconductor substrate having a capacitor contact is provided. Next, a first polysilicon layer is formed. Then, an oxide layer and a silicon oxy-nitride layer are sequentially formed over the first polysilicon layer. Next, the silicon oxy-nitride layer, the oxide layer, and the first polysilicon layer are selectively etched to leave a rectangular stack layer. Afterwards, the oxide layer and the first polysilicon layer of the rectangular stack layer are etched from the sidewall direction to leave a double T-shaped stack layer. Then, second polysilicon layer is formed on the upper surface and the sidewall of the double T-shaped stack layer. Next, the second polysilicon layer is selectively removed. The remaining second and first polysilicon layer are used as the bottom electrode. Afterwards, a dielectric layer and an upper electrode are formed on the bottom electrode.

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Taipei, Taiwan

Tse Yao Huang