Palo Alto Research Center Inc.

Xerox Corporation

Tse Nga Ng

Ping Mei

Gregory Lewis Whiting

Janos Veres

Robert Anthony Street

Jurgen Hans Daniel

Michael L Chabinyc

William S Wong

David Eric Schwartz

Steven E Ready

Sanjiv Sambandan

Bing R Hsieh

Brent Shawhan Krusor

Yiliang Wu

Ana Claudia Arias

John Steven Paschkewitz

Corie Lynn Cobb

Gabriel Iftime

Eugene Michael Chow

Adela Goredema

David Mathew Johnson

Timothy D Stowe

Biby Esther Abraham

Ashish V Pattekar

Jengping Lu

Philipp Helmut Schmaelzle

Rene A Lujan

John E Northrup

Anurag Ganguli

Victor Alfred Beck

George Daniel

Ranjeet Balakrishna Rao

Kye-Si Kwon

Yunda Wang

Pengfei Qi

Sivkheng Kor

Ichiro Fujieda

Leah Lavery

Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed. By these operations, the electronic circuit component is held in a secure attachment by the fixed or cured bonding material, and circuit connections may be made.

Bare die integration with printed components on flexible substrate without laser cut

Disclosed is a conformable, stretchable and electrical conductive structure, which includes an auxetic structure, and a plurality of electrical conductors. The plurality of electrical conductors being incorporated within the auxetic structure, to form conformable, stretchable electrical interconnects, configured based on a design of the auxetic structure and placement of the electrical conductors incorporated with the auxetic structure.

Structural designs for stretchable, conformal electrical interconnects

An organic diode has a substrate, a first conductor layer on the substrate, an organic semiconductor layer on the first conductor layer, and a second conductor layer on the organic substrate layer, wherein one of the conductor layers has an injection enhancement.

Organic Schottky diodes

A structure can include a first layer of a polymer material and a second layer of the polymer material on the first layer, the first and second layers of the polymer material defining a hollow space that was formed by way of a temporary sacrificial structure that was made of a sublimable material.

Forming sacrificial structures using phase-change materials that sublimate

A memory circuit has a ferroelectric memory cell having a word line and a bit line, an input transistor connected to the bit line, a gain element electrically connected the bit line, wherein the gain element includes a feedback capacitor, and an output terminal. A method of reading a memory cell includes applying a voltage to a word line of the memory cell, causing charge to transfer from the memory cell to a feedback capacitor, generating a voltage, amplifying the voltage by applying a gain having a magnitude of less than three, sensing an output voltage at an output node to determine a state of the memory cell, and storing the memory state in a latch.

Memory circuit for reading ferroeletric memory having gain element including feedback capacitor

A sensor network system that includes a sensor array having a plurality of sensor units that include a plurality of sensor elements, each sensor element configured to generate an electrical signal in response to a chemical environment in the vicinity of the sensor unit. The set of electrical signals generated by the sensor elements of the sensor unit represents a measured signature of the environment in the vicinity of the sensor unit. An analyzer is configured to extract the measured signatures of each sensor unit from sensor unit information signals and to detect a presence and concentration of one or more of the gases of interest based on the measured signatures.

Sensor network system

A sensor including a sensing element comprising conductive features formed on a substrate; wherein the conductive features have been formed from a palladium complex ink composition that has been deposited onto the substrate to form the deposited features and wherein the deposited features have been heated to form the conductive features on the substrate. A method including disposing a palladium complex ink composition onto a substrate to form deposited features; and heating the deposited features to form conductive features on the substrate. A strain gauge sensor including a sensing element comprising conductive features formed on a substrate; wherein the conductive features conform to a two dimensional substrate surface; or wherein the conductive features conform to a three dimensional substrate surface.

Sensors comprising palladium complex ink

A thin film device has a source region, a drain region, a first gate disposed between the source region and the drain region, a second gate disposed between the source region and the drain region, wherein the second gate region is in close proximity with the first gate region, a semiconductor film disposed between the source region, the drain region, and the first and second gate regions, and a dielectric material disposed between the source region, the drain region, the first and second gate regions, and the semiconductor film.

Circuit layout for thin film transistors in series or parallel

The level sensor system includes a level sensor label configured to be associated with a container containing a material whose level is to be sensed, the level sensor label arrangement having a circuit which includes an inductive element electrically connected to a capacitive structure configured to be associated with the container.

Printed level sensor

Touch user interfaces have been an essential element in the use of smartphones and tablets. An improved touch or near touch sensing structure made of a printed conductive double-wrapped coil is disclosed. A printable substrate is used to provide a base for the double-wrapped coil. On the printable substrate, a double-wrapped coil is printed using at least one flexible conductive material. The double-wrapped coils can be printed sequentially, simultaneously, parts of the two coils are printed and then the rest of the coil parts are printed, or any other useful printing order. The double-wrapped coil provides an increased sensing area and therefore can compute a more efficient capacitance.

Printed double-wrapped coil on paper for projective capacitance sensing

A transistor has a substrate, source and drain electrodes on the substrate, the source and drain electrodes formed of a conductor ink having silver nanoparticles with integrated dipolar surfactants, an organic semiconductor forming a channel between the source and drain electrodes, the organic semiconductor in contact with the source and drain electrodes, a gate dielectric layer having a first surface in contact with the organic semiconductor, and a gate electrode in contact with a second surface of the gate dielectric layer, the gate electrode formed of silver nanoparticles with integrated dipolar surfactants.

Printable nanoparticle conductor ink with improved charge injection

Embodiments described herein involve methods of forming an interactive card with indicators on a substrate. A plurality of indicators are formed on the substrate by way of a printed electronics process. A plurality of displaceable regions of piezoelectric material are formed on the substrate by way of a printed electronics process. Electrical interconnections are formed on the substrate by way of a printed electronics process, the electrical interconnections connecting an indicator and an associated displaceable region of piezoelectric material such that displacement of the associated displaceable region of piezoelectric material generates a voltage therein that is provided to the indicator in order to actuate the indicator and thereby indicate displacement of the associated displaceable region of piezoelectric material.

Method of fabricating a card with piezo-powered indicator by printed electronics processes

Multiple thin film transistors are aligned in serial and parallel orientation. A second source region is disposed between a first source region and a first drain region. A second drain region is disposed between the first source region and the first drain region. The second drain region and the second source region substantially coincide. A first gate is disposed between the first source region and the coinciding second source and second drain regions. A second gate region is disposed between the first drain region and the coinciding second source and second drain regions. An semiconductor is disposed between the first source region, the first drain region, and the coinciding second source and second drain regions. A dielectric material is disposed between the semiconductor substrate and the first and second gates.

A voltage multiplier includes a supply voltage, at least two multiplier stages electrically connected together, each stage having a trigger voltage terminal, an input terminal, an output terminal, and a capacitor, and each stage connected to the supply voltage, an input stage electrically connected to a first of the at least two multiplier stages, and an output stage electrically connected to a final of the at least two multiplier stages.

Growing community of inventors

Palo Alto, CA, United States of America

Tse Nga Ng