Via Technologies, Inc.

Tse-Hsien Wang

Jiin Lai

Chau-Chad Tsai

Sheng-Chang Peng

Chen-Ping Yang

Chinyi Chiang

Chin-Yi Chiang

Chung-Jui Tseng

A physical layer apparatus compliant for both serial and parallel ATA interfaces is devised. The physical layer apparatus includes a serial ATA physical layer circuit, a channel selection unit and a channel selection controller. The channel selection unit is connected to a media access controller of a host through a first IDE bus. The channel selection unit is further selectively connected to a serial ATA device through the serial ATA physical circuit or connected to a parallel ATA device through second IDE bus. Therefore, the media access controller of the host can selectively access the serial ATA device and the parallel ATA device through the channel selection unit under the control of the channel selection controller.

Physical layer apparatus compliant to serial and parallel ATA interfaces

The present invention discloses an IDE control device suitable for any clock frequency specification. The circuit configuration of the device comprises: a phase-locked loop for receiving clock signals generated from a clock generator and thereby generating a plurality of requested clock signals; and an IDE controller, comprising: a selection module for selecting suitable clock signals and switching active hard discs, and an interface module for generating signals to be transmitted; wherein the selection module is connected to the phase-locked loop and selects clock signals suitable for various hard discs, and then the interface module generates corresponding signals to be transmitted through an IDE bus to access a corresponding hard disc.

IDE control device suitable for supplying a plurality of requested clock signals to various hard discs

A serial ATA control circuit is provided. The control circuit includes a plurality of serial ATA controllers, a plurality of port controlling circuits, a plurality of switch devices, and a switch controller. Each of the serial ATA controllers has a memory accessing controller and two transceivers. The serial ATA control circuit is connected to at least one serial ATA device through the port controlling circuits. The a plurality of port controlling circuits are connected to corresponding serial ATA controllers through the plurality of switch devices controlled by the switch controller. The connection path between each port controlling circuit and corresponding serial ATA controller is selected by the switch controller to achieve optimal data transfer rate.

Serial ATA control circuit for automatically switching connection path

A Circuit for reducing the number of serial ATA external PHY signals includes: a serializer/deserializer, connected to a storage medium controller through a set of parallel signal transmitting lines and a set of parallel signal receiving lines, so as to convert signals between parallel and serial specifications; a phase locked loop, connected to the serializer/deserializer so as to generate a clock signal required for data signal transmission; at least one pair of transmitter and receiver, each connected to the serializer/deserializer, each transmitter able to transmit the serial data signal from the serializer through a set of serial signal transmitting lines to a serial ATA device, and each receiver able to receive the serial data from the serial ATA device through a set of serial signal receiving lines to the deserializer; and at least one OOB signal detector, each connected to the corresponding receiving lines, so as to detect the out of band signals from the serial ATA device. The Circuit also employs in certain applications a signal encoding approach for reducing the number of serial ATA external PHY signals, wherein an encoder and a decoder are employed to encode control signals and status signals into special data codes transmitted between a serial ATA external PHY and a storage medium controller, so as to minimize the number of interface signals.

Circuit and signal encoding method for reducing the number of serial ATA external PHY signals

A conversion circuit is devised to convert burst signals referencing to a plurality of clocks, respectively. A burst signal referencing to a first clock is decomposed into a plurality of non-burst signals by a plurality of phase signal generators and corresponding signal fetching units. The plurality of non-burst signals are converted to signals referencing a second clock by a plurality of converters and those signals are synthesized into an output signal by a synthesizer. Therefore, the burst signal referencing to the first clock can be converted to the burst signal referencing to the second clock.

Conversion circuit for burst signals referencing to various clocks and method for the same

A method of conducting delayed data transaction on a PCI system and its associated devices. The delayed data transaction is carried out using a PCI system to transmit data between an initiator and a responder. Both the initiator and the responder are coupled to a PCI bus. The delayed transaction in the PCI system includes a number of steps. To begin with, the initiator will send out a request to use the PCI bus so that data transmission can be conducted with respect to the responder. If the responder accepts the request but unable to secure the requested data soon enough, the responder will generate a defer identifier that corresponds to the requesting initiator. Next, a stop signal and the defer identifier generated by the responder will be returned to the initiator, indicating that the request has been accepted. When the requested data is ready in the responder, the responder will forward the defer identifier again. The initiator picks up the defer identifier and prepares according to the buffer identifier in it. Then, data transmission between the initiator and the responder begins.

PCI system controller capable of delayed transaction

A method for controlling a FIFO array. The method uses a write pointer to indicate a write address, a read pointer to indicate a read address, a flag to indicate the status of the write pointer and the read pointer, and a number of status parameters to indicate the status of the FIFO array. The FIFO array has M addresses, and a first address is one of the M addresses. When both the write pointer and the read pointer point to the first address of the FIFO array and a write data operation is performed, the flag is a first value and the write pointer points to the next address following the first address of the FIFO array. When both the read pointer and the write pointer point to the first address of the FIFO array and a read data operation is performed, the flag is a second value and the read pointer points to the next address following the first address of the FIFO array. Finally, status parameters are set. By these, the FIFO array is easily and effective controlled in various situations.

Method for controlling a first-in-first-out array to facilitate data transmissions between a lower frequency domain and a higher frequency domain of a computer system

A delayed transaction method and system to handle multiple delayed transactions in a PCI system is disclosed. When the responder accepts a first and second request from an initiator but can not immediately respond to the first and second request, the responder generates a first and a second defer identifier corresponding to the initiator, respectively. When data transfer between the responder and the initiator corresponding to the first request is completed and data is ready for transfer corresponding to the second request, the responder immediately issues a second buffer identifier along with the data requested corresponding to the second request. Thus, data transfer between the initiator and the responder based on the second buffer identifier corresponding to the second request can proceed.

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Taipei, Taiwan

Tse-Hsien Wang