Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsann Lin

Ji-Feng Ying

Chung-Te Lin

Han-Ting Tsai

Jhong-Sheng Wang

Wei-Gang Chiu

Min-Kun Dai

Ya-Ling Lee

Cheng-Yi Wu

I-Cheng Chang

Han-Jong Chia

Jui-Fen Chien

Chih-Chung Lai

Chien-Min Lee

Yen-Chieh Huang

Kuo-Chang Chiang

Yu-Ming Lin

Rainer Yen-Chieh Huang

Hanwen Yeh

I Cheng Chang

A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.

Transistor including a hydrogen-diffusion barrier and methods for forming the same

Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.

Crystal seed layer for magnetic random access memory (MRAM)

A magnetic memory includes a first spin-orbital-transfer-spin-torque-transfer (SOT-STT) hybrid magnetic device disposed over a substrate, a second SOT-STT hybrid magnetic device disposed over the substrate, and a SOT conductive layer connected to the first and second SOT-STT hybrid magnetic devices. Each of the first and second SOT-STT hybrid magnetic devices includes a first magnetic layer, as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.

Magnetic device and magnetic random access memory

An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

Memory device and method for fabricating the same

The present disclosure provides a method for characterizing magnetic properties of a target layer, including providing a first sample having a first structure, providing a second sample having a target layer over the first structure, obtaining a first magnetic property of the first sample, obtaining a second magnetic property of the second sample, and deriving a third magnetic property of the target layer according to the first magnetic property and the second magnetic property.

Method for characterizing magnetic device

A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a hard bias layer, a reference layer disposed over the hard bias layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer wherein the diffusion barrier layer comprises an amorphous and nonmagnetic film of a form X-Z, where X is Fe or Co and Z is Hf, Y, or Zr. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.

Magnetic tunnel junction (MTJ) element and its fabrication process

In an embodiment, a device includes: a magnetoresistive random access memory cell including: a bottom electrode; a reference layer over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lesser coercivity than the reference layer; a cap layer over the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a greater atomic concentration of oxygen and a lesser atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode over the cap layer.

Magnetic tunnel junction devices

A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.

Memory device and semiconductor die, and method of fabricating memory device

Provided is a method of forming a ferroelectric memory device including: forming a ferroelectric layer between a gate electrode and a channel layer by a first atomic layer deposition (ALD) process. The first ALD process includes: providing a first precursor during a first section; and providing a first mixed precursor during a second section, wherein the first mixed precursor includes a hafnium-containing precursor and a zirconium-containing precursor. In this case, the ferroelectric layer is directly formed as HfZrOwith an orthorhombic phase (O-phase) to enhance the ferroelectric polarization and property.

Method of forming ferroelectric memory device

A method of forming a semiconductor structure includes following operations. A memory layer is formed over the first gate electrode. A channel layer is formed over the memory layer. A first SUT treatment is performed. A second dielectric layer is formed over the memory layer and the channel layer. A source electrode and a drain electrode are formed in the second dielectric layer. A temperature of the first SUT treatment is less than approximately 400° C.

Semiconductor structure and method of forming the same

A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a reference layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.

Some embodiments relate to a method for manufacturing a memory device. The method includes forming a bottom electrode layer over a substrate. A first etch process is performed, thereby defining one or more holes in the bottom electrode layer and defining a bottom electrode. A pair of insulators are formed within the one or more holes such that the insulators are disposed on opposing sides of the bottom electrode. A buffer layer, a seed layer, a magnetic tunnel junction (MTJ) stack, and a top electrode are formed over the bottom electrode. A second etch process is performed to remove a portion of the buffer layer, the seed layer, the MTJ stack, and the top electrode, thereby defining a memory cell.

Magnetic tunneling junction (MTJ) element with an amorphous buffer layer and its fabrication process

A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a buffer layer, a seed layer disposed over the buffer layer, a reference layer disposed over the seed layer, a tunnel barrier layer disposed over the reference layer and a free layer disposed over the tunnel barrier layer. The seed layer includes a Cobalt (Co)-based film. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.

Growing community of inventors

Hsinchu, Taiwan

Tsann Lin