Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Tsan-Chun Wang

Chun Hsiung Tsai

Ziwei Fang

Chun-Feng Nieh

Su-Hao Liu

Liang-Yin Chen

Huicheng Chang

Yu-Cheng Chen

Chiao-Ting Tai

Tze-Liang Lee

Kei-Wei Chen

De-Wei Yu

Lun-Kuang Tan

Jing-Huei Huang

Yee-Chia Yeo

Syun-Ming Jang Jang

Chao-Cheng Chen

Chii-Horng Li

Kuo-Hsing Cheng

Yi-Fan Chen

Chun-Chi Lai

Ching-Wei Chen

Chii-Ming M Wu

Tsz-Mei Kwok

Chun-Hsiung Tsai

Zi-Wei Fang

Chih-Hung Lin

Wan-Yu Lo

Maw-Song Chen

Yi-Hui Li

Che-Fu Chiu

Yu-Lien Huang

Ching-Huan Lin

Da-Wen Lin

Hsiang-Lin Lin

Yao-Jen Hsieh

Wei-Ming Huang

Chien-Tai Chan

Chih-Hung Shih

Kuo-Yu Huang

Chia-Ling Chan

Ke-Chih Chang

Lai-Wan Chong

Tung-Huang Chen

Chii-Meng Wu

Chung-Feng Nieh

A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.

Gate structure of semiconductor device and method of manufacture

A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.

Manufacturing method of fin-type field effect transistor structure

A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

Sacrificial layer for semiconductor process

A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space. Fluorine is implanted into the gate sidewall spacers and the fin after forming the high-k gate dielectric layer by performing a second fluorine implantation.

Method for fabricating a semiconductor device

In a method for manufacturing a semiconductor device, fin structures each having an upper portion and a lower portion, are formed. The lower portion is embedded in an isolation insulating layer disposed over a substrate and the upper portion protrudes the isolation insulating layer. A gate dielectric layer is formed over the upper portion of each of the fin structures. A conductive layer is formed over the gate dielectric layer. A cap layer is formed over the conductive layer. An ion implantation operation is performed on the fin structures with the cap layer. The ion implantation operation is performed multiple times using different implantation angles to introduce ions into one side surface of each of the fin structures.

Method of manufacturing semiconductor devices

In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.

Process for making multi-gate transistors and resulting structures

Fin-type field effect transistor structure and manufacturing method thereof

A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor structure over a semiconductor substrate. The method also includes implanting carbon into the semiconductor structure. The method further includes implanting gallium into the semiconductor structure. In addition, the method includes heating the semiconductor structure after the implanting of carbon and gallium.

Formation of semiconductor device structure by implantation

The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

Method to reduce etch variation using ion implantation

Growing community of inventors

Hsinchu, Taiwan

Tsan-Chun Wang