Freescale Semiconductor,inc.

Nxp Usa, Inc.

Trung Duong

Michael B Vincent

Scott M Hayes

Zhiwei Gong

Weng Foong Yap

Douglas G Mitchell

Alan J Magnus

Jason R Wright

Robert Joseph Wenzel

Gilles Montoriol

Nishant Lakhera

Akhilesh Kumar Singh

Eduard Jan Pabst

Navas Khan Oratti Kalandar

Ilan Lidsky

Embodiments are provided herein for a packaged semiconductor device and method of fabricating, the device including: a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and a support structure including an attachment portion and two or more standing members extending from an inner surface of the attachment portion, wherein a back side of the package body is attached to the inner surface of the attachment portion.

Package with support structure

Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers

Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

Microelectronic packages having layered interconnect structures and methods for the manufacture thereof

A structure includes a semiconductor die that has an arrangement of die pads on a surface of the semiconductor die. A first row of die pads consists of a first group of four die pads and run in a first direction. A second row of die pads are adjacent to the first row and consist of a second group of four die pads running in the first direction. The second row begins at a first offset in the first direction from where the first row begins. A third row of die pads are adjacent to the second row and comprise a third group of four die pads that run in the first direction. The third row begins at a second offset in the first direction from where the second row begins. This allows for relatively easy access to all of the die pads.

Semiconductor die with die pad pattern

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Austin, TX, United States of America

Trung Duong