Intel Corporation

Tracy Garrett Drysdale

Elmoustapha Ould-Ahmed-Vall

Thomas Willhalm

Robert Valentine

Gilbert A Neiger

Mark Jay Charney

Jesus Corbal

Rajesh M Sankaran

Edward Thomas Grochowski

Eriko Nurvitadhi

Koichi Yamada

Thomas D Fletcher

Joseph Nuzman

Deborah T Marr

Stephen R Van Doren

Dennis Ryan Bradford

Paul Caprioli

Lokpraveen B Mosur

Narayan Ranganathan

Kent D Glossop

Niall D McDonnell

Jonathan D Pearce

Richard J Greco

Ganesh Venkatesh

Jeffrey J Cook

Asit K Mishra

Dwight P Manley

David B Sheffield

Nicholas P Carter

Michael A O'Hanlon

Vinodh Gopal

James D Guilford

Gilbert M Wolrich

Scott P Bobholz

Sitaram Yadavalli

James T Kukunas

Husnara Khan

Niall D Mcdonnell

Michael A O'HANLON

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Systems, methods, and apparatuses for heterogeneous computing

Systems, apparatuses, and methods for performing delta decoding on packed data elements of a source and storing the results in packed data elements of a destination using a single packed delta decode instruction are described. A processor may include a decoder to decode an instruction, and execution unit to execute the decoded instruction to calculate for each packed data element position of a source operand, other than a first packed data element position, a value that comprises a packed data element of that packed data element position and all packed data elements of packed data element positions that are of lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of a destination operand, and for each calculated value, store the value into a corresponding packed data element position of the destination operand.

Systems, apparatuses, and methods for performing delta decoding on packed data elements

Methods and apparatuses relating to offload operations are described. In one embodiment, a hardware processor includes a core to execute a thread and offload an operation; and a first and second hardware accelerator to execute the operation, wherein the first and second hardware accelerator are coupled to shared buffers to store output data from the first hardware accelerator and provide the output data as input data to the second hardware accelerator, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator with a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator with an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator with a corresponding response entry for each respective shared buffer.

Hardware accelerators and methods for offload operations

Methods and apparatuses relating to stateful compression and decompression operations are described. In one embodiment, hardware processor includes a core to execute a thread and offload at least one of a compression and decompression thread, and a hardware compression and decompression accelerator to execute the at least one of the compression and decompression thread to consume input and generate output data, wherein the hardware compression and decompression accelerator is coupled to a plurality of input buffers to store the input data, a plurality of output buffers to store the output data, an input buffer descriptor array with an entry for each respective input buffer, an input buffer response descriptor array with a corresponding response entry for each respective input buffer, an output buffer descriptor array with an entry for each respective output buffer, and an output buffer response descriptor array with a corresponding response entry for each respective output buffer.

Hardware accelerators and methods for stateful compression and decompression operations

Examples of systems, apparatuses, and methods for performing delta encoding on packed data elements of a source and storing the results in packed data elements of a destination using a single vector packed delta encode instruction are described.

Systems, apparatuses, and methods for performing delta encoding on packed data elements

Embodiments of systems, apparatuses, and methods for performing delta encoding on packed data elements of a source and storing the results in packed data elements of a destination using a single vector packed delta encode instruction are described.

Various methods, apparatuses, and systems that use a replacement policy algorithm to implement tracking of one or more memory locations that have incurred one or more data transfer failures.

Various methods and apparatuses to track failing memory locations to enable implementations for invalidating repeatedly failing memory locations

A method and apparatus for synchronizing and communicating between processing entities, such as cores or threads, in a multiprocessor. Two registers are used as a 'hardware mailbox' by two processing entities of a microprocessor. A first register is used to communicate information from a first processing entity to a second processing entity, while a second register is used to communication information from the second processing entity to the first processing entity. The first and second registers are cross-decoded by the two processing entities. One or more bits in each register are used to synchronize operation of the processing entities. In a microprocessor including three or more such processing entities, a read-write register of each processing entity holds outgoing information and a read-only register of each processing entity holds incoming information. A separate logic circuit logically combines the contents of the read-write registers and stores the result in the read-only registers.

Method and apparatus for communicating between processing entities in a multi-processor

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Paradise Valley, AZ, United States of America

Tracy Garrett Drysdale