Mitsubishi Denki Kabushiki Kaisha

Toshiyuki Toyoshima

Takeo Ishibashi

Naoki Yasuda

Suguru Nagae

Teruhiko Kumada

Hideharu Nobutoki

Keiichi Katayama

Hirofumi Fujioka

Ayumi Minamide

Toshio Kobayashi

Shin Hasegawa

Takayuki Saito

Masanobu Iwasaki

Kouichirou Tsutahara

Junjiro Sakai

Satoshi Yanaura

Yoshiharu Ono

Tadashi Miyagi

Kanji Sugino

Yasuo Furuhashi

A low dielectric constant material having an excellent water resistance obtained by heat-treating a borazine compound of the formula (1-2): or an inorganic or organic compound having a group derived from the borazine compound (1-2) to undergo a condensation reaction, thereby producing an oligomer or polymer, wherein Rto Rare independently a hydrogen atom, an alkyl group having 1 to 20 carbon atoms, an aryl group, a substituted aryl group, an alkenyl group, an amino group, an alkylamino group, an alkoxyl group, a thioalkoxyl group, a carbonyl group, a silyl group, an alkylsilyl group, a phosphino group, an alkylphosphino group, or a group of the formula: Si(OR)(OR)(OR), and at least one of Rto Ris not hydrogen atom.

Source material for preparing low dielectric constant material

Method of producing a multi-layered wiring board comprising the steps of subjecting the photosensitive resin to exposure- and development-treatment to form the holes having a predetermined size and shape; depositing and forming the curable resin to the insulating layer having the holes formed therein in such a manner as to bury the holes, and conducting heat-treatment to form the cured thin film of the curable resin on the surface of the insulating layer; and so removing the curable resin as to leave the cured thin film to obtain the via-holes having the reduced opening size by the cured thin film.

Method of producing a multi-layered wiring board

A via-filling material includes a polymer containing a repeating unit represented bywherein Rone of hydrogen, fluorine, chlorine, bromine, and methyl group; Ris one of hydrogen, a Calkyl group, and a Calkyl group in which the hydrogen is replaced by at least one of fluorine, chlorine, and bromine; and X is &#x2014;C(&#x2550;O)O&#x2014; or &#x2014;S(&#x2550;O)O&#x2014;. This via-filling material does not generate deposits around an opening of a via hole during plasma etching and provides a semiconductor integrated circuit with high reliability, even when a trench wider than the via hole is formed by plasma etching around the via hole filled with the via-filling material.

Via-filling material and process for fabricating semiconductor integrated circuit using the material

A low dielectric constant material having excellent water resistance comprising a borazine skeleton structure represented by any one of the formulas (2) to (4):wherein Rto Rare independently a hydrogen atom, an alkyl group having 1 to 20 carbon atoms, an aryl group, a substituted aryl group, an alkenyl group, an alkylamino group, an alkoxyl group, a thioalkoxyl group, a carbonyl group, a silyl group, an alkylsilyl group, a phosphino group, an alkyiphosphino group, or a group of the formula: Si(OR)(OR)(OR), provided that at least one of Rto Ris not a hydrogen atom.

Low dielectric constant material, insulating film comprising the low dielectric constant material, and semiconductor device

An electronic device assembled using a coupler which has an electroconductive region and a resin region on the surface. Flexibility of the resin region absorbs stress caused by difference in thermal expansion coefficient between an organic printed circuit board and a semiconductor chip through the deformation of the electroconductive region. As a result, formation of cracking in the coupler is avoided. It is preferable that the resin region occupies from 20 to 80% of the total surface area of the coupler. The coupler may be formed from a molten blend of the heat resistant resin and a joining metal. The coupler may also be formed by molding a blend of the heat resistant resin and metal powder, wherein the metal powder locating on the surface of the coupler have a joining metal joined thereto.

Electronic device and coupler

A method of fabricating a capacitor includes selectively forming a positive photosensitive resin layer on a first conductive layer; exposing the positive photosensitive resin layer, immersing the exposed positive photosensitive resin layer in a solution in which dielectric particles are dispersed and diffusing the dielectric particles into the positive photosensitive resin layer; forming an insulating resin layer covering side faces of the positive photosensitive resin layer; and forming a second conductive layer on the positive photosensitive resin layer. According to the method, a very reliable capacitor having excellent electrical characteristics, such as dielectric strength, can be cheaply and easily fabricated in a wiring layer.

Method of fabricating capacitor having a photosensitive resin layer as a dielectric

A resist pattern, containing a material capable of generating an acid by exposure to light, is covered with a resist containing a material capable of crosslinkage in the presence of an acid. The acid is generated in the resist pattern by application of heat or by exposure to light, and a crosslinked layer is formed at the interface as a cover layer for the resist pattern, thereby causing the resist pattern to be thickened. Thus, the hole diameter of the resist pattern can be reduced, or the isolation width of a resist pattern can be reduced.

Material for forming a fine pattern and method for manufacturing a semiconductor device using the same

The object of the present invention is to provide a polishing agent for processing semiconductor, which can control coagulation and sedimentation and has stable and re-productive polishing properties under a proper dispersing condition to prevent generation of polishing flaw. The polishing agent for processing semiconductor comprises a compound having glucose structure, polishing particles and water.

Polishing agent for processing semiconductor, dispersant used therefor and process for preparing semiconductor device using above polishing agent for processing semiconductor

There is described a method of producing a pure resist pattern having superior topography smaller than the limit of wavelength of exposure light. A first resist pattern containing material capable of producing an acid on exposure to light is coated with a second resist containing material which causes a crosslinking reaction in the presence of an acid. An acid is produced in the resist pattern by exposing the pattern to light, thus forming a crosslinked layer along the boundary surface between the first resist pattern and the second resist. As a result, a second resist pattern which is greater than the first resist pattern is formed. Minute pure resist patterns are produced through two-step processing: that is, by removing the second resist from the substrate through use of a liquid prepared by dissolving an organic solvent into water and by rinsing the substrate with water. The diameter of holes formed in the resist or the interval between isolated patterns can be reduced.

Method of manufacturing a semiconductor device using a minute resist pattern, and a semiconductor device manufactured thereby

There is described a method of stably manufacturing a fine resist pattern narrower than the wavelength of exposing light from a stepper. Under the method, a resist pattern is formed on a semiconductor substrate through use of an acid catalyst chemically-amplified photoresist, and an organic film which includes an acid or which produces an acid on exposure to light is formed on the surface of the semiconductor substrate including the resist pattern. The organic film is then subjected to a heat treatment to thereby diffuse an acid. The surface layer of the resist pattern is made soluble in an alkaline developer, and the surface layer of the resist pattern is removed through use of the alkaline developer. As a result, a fine resist pattern is formed.

Method of manufacturing a semiconductor device having a fine pattern, and semiconductor device manufactured thereby

A first resist pattern, which is capable of generating an acid, is formed on a semiconductor device layer. Over the first resist pattern, a layer of a second resist, which is capable of undergoing an cross-linking reaction in the presence of an acid, is formed. Then, a cross-linked film is formed in portions of said layer of the second resist at the boundary with said first resist by action of an acid from said first resist. Thereafter, non-cross-linked portions of said second resist are removed to form a finely isolated resist pattern. The semiconductor device layer is etched, via a mask of said finely isolated resist pattern, to form a fine spaces or holes.

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Tokyo, Japan

Toshiyuki Toyoshima