Hitachi, Ltd.

Texas Instruments Corporation

Hitachi Vlsi Engineering Corp.

Intel Corporation

Toshiyuki Sakuta

Gen Murakami

Masamichi Ishihara

Kazuya Ito

Satoshi Oguchi

Kazuyuki Miyazawa

Tomohiro Suzuki

Kunihiko Nishi

Aizo Kaneda

Shozo Nakamura

Masao Mitani

Hidetoshi Iwai

Masanori Tazunoki

Hisashi Nakamura

Yasuhiro Kasama

Eiji Miyamoto

Yutaka Ito

Yasushi Takahashi

Ichiro Anjoh

Kanji Otsuka

Hiroshi Satoh

Yasunori Yamaguchi

Masao Kawamura

Takumi Nasu

Tetsu Udagawa

Makoto Homma

Shigeo Kuroda

Wai Lee

Hiromi Matsuura

Toshiaki Minami

Kunizo Sahara

Makoto Kuwata

Shigetoshi Sakomura

Hinoko Kurosawa

Toshihiko Satoh

Minoru Enomoto

Keiji Sasaki

Hiromitsu Mishimagi

Youichi Matsuno

Atsusi Nozoe

Yuriko Iizuka

Kazuhiko Kajigaya

Hiroyuki Uchiyama

Yoshinobu Nakagome

Ryoichi Hori

Kunihiro Tsubosaki

Toshio Sasaki

Kazuyoshi Oshima

Hitoshi Tanaka

Toshitsugu Takekuma

Masaya Muranaka

Satoru Ito

Yukihide Suzuki

Eric R Wehage

Toshio Maeda

Osamu Sakai

Eiji Yamasaki

Wataru Arakawa

Michael J Greger

Yasuo Mori

Nao Miyamoto

Tomoshi Matsumoto, Deceased

Yutaka Itou

In a semiconductor device having the upmost wiring layer comprised of aluminum and the wiring layer immediately below it comprised of copper, the upmost wiring layer is made thicker than the wiring layer immediately below it so that the upmost wiring layer is lower in sheet resistance than the wiring layer immediately below it. Multiple ring power lines VR and pads PD are formed of the upmost wiring layer, and the ring power lines VR and the pads PD are connected respectively through power lines VLBof the upmost wiring layer. Consequently, the voltage drop on the power feed path from the pads PD to the ring power lines VR can be reduced and the power conduction from the pads PD to the ring power lines VR can be stabilized.

Semiconductor device

The present invention provides a semiconductor integrated-circuit device capable of achieving higher-density integration and faster operation, and a CMOS circuit operational speeding-up method for easily achieving the operating speeds of CMOS circuits, including existing one. A signal transferring path includes a plurality of CMOS-constructed logic gate circuits provided between one pair of flip-flop circuits for acquiring and holding signals by use of clock signals. The signal transferring path includes a first and a second signal transferring path. The first signal transferring path is constituted by enhancement-type MOSFETs and has a signal transferring delay time equal to, or less than, a permissible signal transferring delay time. The second signal transferring path is configured such that, among the above-mentioned plurality of logic gate circuits, a logic gate circuit having a delay time longer than the above-mentioned permissible signal transferring delay time when constituted using enhancement-type MOSFETs is replaced with a depletion-type MOSFET so that the second signal transferring path may provide a signal transferring delay time equal to or less than the permissible signal transferring delay time mentioned above.

Semiconductor integrated-circuit device and method to speed-up CMOS circuit

In a semiconductor device having the upmost wiring layer comprised of aluminum and the wiring layer immediately below it comprised of copper, the upmost wiring layer is made thicker than the wiring layer immediately below it so that the upmost wiring layer is lower in sheet resistance than the wiring layer immediately below it. Multiple ring power lines VR and pads PD are formed of the upmost wiring layer, and the ring power lines VR and the pads PD are connected respectively through power lines VLB of the upmost wiring layer. Consequently, the voltage drop on the power feed path from the pads PD to the ring power lines VR can be reduced and the power conduction from the pads PD to the ring power lines VR can be stabilized.

A digital multiplier for multiplying a plurality of multiplicand signals X -X representing a multiplicand and a plurality of multiplier signals Y -Y representing a multiplier. In it, a plurality of intermediate results signals, such as partial product signals, are generated from the multiplicand signals and the multiplier signals. A plurality of adder circuits are also provided for adding the intermediate results signals to generate a plurality of final result signals representing the result of multiplying the multiplicand and the multiplier, wherein at least some of the adder circuits receive first signals representing intermediate addition results from at least two prior adder stages and also receive second signals representing intermediate results generated as the result of only a single addition. Finally, a plurality of delay elements are placed in selected second signal lines so as to delay the arrival of the second signals to the at least some of the adder circuits so as to synchronize the arrival of the inputs to the at least some of the adder circuits.

Low power multiplier

A local integrated circuit device provides remote configuration access to one or more remote integrated circuit devices. The local integrated circuit device receives configuration access requests through at least two interfaces. The local integrated circuit device accesses a configuration space of one or more remote integrated circuit devices in accordance with the received configuration access requests.

Remote configuration access for integrated circuit devices

A digital multiplier 110 for multiplying a plurality of multiplicand signals X0-X23 representing a multiplicand and a plurality of multiplier signals Y0-Y23 representing a multiplier. In it, a plurality of intermediate results signals, such as partial product signals, are generated from the multiplicand signals and the multiplier signals. A plurality of adder circuits 40 are also provided for adding the intermediate results signals to generate a plurality of final result signals representing the result of multiplying the multiplicand and the multiplier, wherein at least some of the adder circuits receive first signals representing intermediate addition results from at least two prior adder stages and also receive second signals representing intermediate results generated as the result of only a single addition. Finally, a plurality of delay elements 70 are placed in selected second signal lines so as to delay the arrival of the second signals to the at least some of the adder circuits so as to synchronize the arrival of the inputs to the at least some of the adder circuits.

A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.

A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.

Sealed stacked arrangement of semiconductor devices

A voltage generating circuit in a semiconductor integrated circuit driven by two sorts of power supply voltages, includes a unit for generating plural sorts of signals; a unit for selecting one of the plural sorts of signals in response to an operation mode of the semiconductor integrated circuit; and a pumping unit for producing either a first predetermined voltage higher than the high power supply voltage among the two sorts of power supply voltages, or a second predetermined voltage lower than the low power supply voltage by a pumping operation based upon the signal selected by the selecting unit.

Voltage generating circuit in semiconductor integrated circuit

A semiconductor device in which shield wiring is arranged between the semiconductor substrate and the power source wiring for supplying the power source potential or ground potential. Noise, as represented by variations in the potential of the semiconductor substrate, is substantially prevented from transferring to the aforementioned power source wiring by the shield wiring. In one aspect, shield wiring 1 is arranged between Vss wiring for supplying potential to the various circuits on the semiconductor substrate and substrate 7. This shield wiring 1 is connected to grounding lead frame 18 via M1 intra-chip wiring 4, M2 intra-chip wiring 5, connecting part 40, bonding pad 3 and bonding wire 8. Since the coupling impedance between shield wiring 1 and substrate 7 (due almost solely to the electrostatic capacitance Css) is large, and coupling impedance between Vss wiring 2 and substrate 7 (due almost solely to the junction capacitance D) is low, the noise caused by variations in the potential of substrate 7 is transferred to shield wiring 1, while it is not appreciably transferred to Vss wiring 2.

Semiconductor device having shield wiring for noise suppression

A voltage generating circuit for providing a prescribed voltage, such as 1/2V.sub.DD of the power source voltage V.sub.DD, wherein the capacity of the current and the response time of the voltage generating circuit is significantly improved. When the output voltage V.sub.OUT of the voltage generating circuit drops suddenly from a reference value 1/2V.sub.DD and goes below the lower limit of an allowable voltage level VM-, an n-type MOS transistor MN5A of an output voltage detecting circuit 14 turns on. The potential of the gate terminal for a p-type MOS transistor MP6A in a digital output circuit 16 is pulled to the level of the output voltage V.sub.OUT via the transistor MN5A that was turned on, and said p-type MOS transistor MP6A is turned on in the saturated area more or less perfectly. By virtue of a large amount of current flowing to the output side of a terminal side, namely the load circuit side, at an appropriate voltage from a power source terminal 18 via p-type MOS transistor MP6A which was turned on in the saturated area, a reduction in output voltage V.sub.OUT is stopped quickly and the output voltage is restored to the normal level within a short time.

Voltage generating circuit

A semiconductor memory device capable of a self-refreshing operation with a refresh-initiation signal generated in the memory device has a self-refreshing control circuit. A self-refreshing operation is automatically effected, without externally supplied clock signals, with a specific refreshing cycle having an internally set mode entry time period, a burst refresh time period and an internally set pause time period. These time periods are detected by a single counter circuit arranged to count pulses produced from a basic clock pulse signal generated by an oscillator. The burst refreshing is effected with the pulses contained in a pulse signal generated in synchronization with the basic clock pulse signal from the oscillator.

Semiconductor memory device having a self-refreshing control circuit

A dynamic RAM provided with a data retention mode intended for low power consumption is provided. In the data retention mode, the current supply capabilities of voltage generation circuits which generate decreased voltage, increased voltage, reference voltage, etc., are limited in the range in which information retention operation in memory cells can be maintained, and the number of selected memory mats in the data retention mode is increased with respect to that of memory mats selected in the normal read/write mode and refresh mode. Special modes such as the data retention mode are set by combining an address strobe signal and other control signals and dummy CBR refresh is executed to release the special mode.

Special mode control method for dynamic random access memory

Growing community of inventors

Hamura, Japan

Toshiyuki Sakuta