Adv Antest Corporation

Tohoku University

The Furukawa Electric Co., Ltd.

Toshiyuki Okayasu

Daisuke Watanabe

Kazuhiro Yamamoto

Masakatsu Suda

Atsushi Ono

Shoji Kojima

Shigetoshi Sugawa

Akinobu Teramoto

Masashi Shibata

Masahiro Ishida

Shinya Sato

Satoshi Sudou

Nobuhito Kishi

Akihiro Fujimoto

Satoshi Iwamoto

Tsutomu Akiyama

Masatoshi Ohashi

Shinichi Yokota

Kazuhiro Fujita

Masatoshi Sato

Kiyotaka Ichiyama

Takashi Sekino

Hiroo Suzuki

Masahiro Yamakawa

Toshiaki Awaji

Masayuki Kawabata

Yoshiharu Umemura

Hiroshi Tsukahara

Nobusuke Seki

Yusuke Hayase

A main power supply supplies a power supply voltage to a power supply terminal of a DUT. A control pattern generator generates a control pattern including a pulse sequence. A compensation circuit intermittently injects a compensation current to the power supply terminal of the DUT via a path different from that of the main power supply. A switch is arranged between an output terminal of a voltage source and the power supply terminal of the DUT, and is turned on and off according to the control pattern.

Test apparatus and testing method

A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR.

Test apparatus with voltage margin test

A test apparatus that tests a plurality of devices under test formed on a wafer under test includes a test substrate that faces the wafer under test and is electrically connected to the devices under test, a programmable device that is provided on the test substrate and changes a logic relationship of output logic data with respect to input logic data, according to program data supplied thereto, a plurality of input/output circuits that are provided on the test substrate to correspond to the devices under test and that each supply the corresponding device under test with a test signal corresponding to the output logic data of the programmable device, and a judging section that judges pass/fail of each device under test, based on operation results of each device under test according to the test signal.

Test apparatus and manufacturing method

An amplitude expected value data generator generates amplitude expected value data that represents, in increments of sampling points, which of multiple amplitude segments the amplitude of a modulated signal waveform that corresponds to the expected value of data to be output from a device under test belongs to. A demodulator performs sampling of the signal waveform to be tested received from the device under test, and generates judgment data that represents, in increments of sampling points, which of the multiple amplitude segments the amplitude of the signal waveform belongs to. A judgment unit makes a comparison between the amplitude expected value data and the judgment data in increments of sampling points.

Test apparatus for digital modulated signal

Provided is an electronic device that generates an output signal corresponding to an input signal, comprising a signal processing section that receives the input signal and outputs the output signal corresponding to the input signal, and a floating electrode that accumulates a charge by being irradiated by an electron beam. The signal processing section adjusts electric characteristics of the output signal according to a charge amount accumulated in the floating electrode, and includes a transistor formed on the semiconductor substrate between an input terminal that receives the input signal and an output terminal that outputs the output signal. The floating electrode is formed between a gate electrode of the transistor and the semiconductor substrate.

Electronic device and manufacturing method

Provided is a test wafer unit that tests a plurality of circuits under test formed on a wafer under test. The test wafer unit comprises a test wafer that is formed of a semiconductor material and exchanges signals with each of the circuits under test, and a plurality of loop-back sections that are provided in the test wafer to correspond to the plurality of circuits under test and that each supply the corresponding circuit under test with a loop-back signal corresponding to a signal received from the corresponding circuit under test.

Wafer unit for testing and test system

A test system includes a test substrate that transmits/receives signals to/from a semiconductor wafer, and a control apparatus to control the test substrate. The semiconductor wafer includes an external terminal coupled to an external measurement circuit, a plurality of selecting wiring lines provided to receive/transmit signals to/from the corresponding the measuring points, and a selecting section that selects one of the selecting wiring lines and that allows signal transmission between the corresponding measuring point and the external terminal through the selected selecting wiring line. The test substrate includes a measurement circuit that is coupled to the external terminal of the semiconductor wafer and that measures an electrical characteristic of a signal transmitted through the selecting wiring line selected by the selecting section, and a control section that controls which one of the measurement wiring lines is to be selected by the selecting section in the semiconductor wafer.

Semiconductor wafer, semiconductor circuit, substrate for testing and test system

A data signal is transmitted synchronously with a clock signal, and contains n phases (n represents an integer of 2 or more) of data for each cycle of the clock signal. A first time to digital converter generates clock change point information which represents the change timing of the clock signal. A second time to digital converter receives a data sequence in increments of cycles of the clock signal, and generates data change point information items which represent the change timing of the data in increments of phases of the data. A calculation unit calculates difference data between the change timing represented by the data change point information and the change point timing represented by the clock change point information in increments of phases. A judgment unit judges a DUT based upon the difference data received from the calculation unit.

Test apparatus and test method

A change-point detection circuitextracts a clock signal from serial data, input data. A variable delay circuit provides a delay in accordance with a delay control signal to a reference signal having a predetermined frequency, so that the phase of the reference signal is shifted on the basis of an initial delay. An input latch circuit latches internal serial data by using an output signal of the variable delay circuit as a strobe signal. A phase comparator matches the frequencies of the clock signal and the strobe signal with each other, and generates phase difference data in accordance with a phase difference between the two signals. A loop filter integrates the phase difference data generated by the phase comparator and outputs it as the delay control signal. The phase shift amount acquisition unit acquires a phase shift amount based on the delay control signal, the phase shift amount being based on the initial delay provided to the reference signal by the variable delay circuit.

Clock data recovery circuit and method

A test apparatus includes: a driver circuit that supplies, to a device under test, a test signal corresponding to an input signal; and a judging section that judges pass/fail of the device under test, based on the load voltage or the load current supplied to the device under test when supplying a test signal of a constant current or a constant voltage to the device under test from the driver circuit, where the driver circuit includes: a driver section that outputs the test signal; a supply current detecting section that detects a supply current supplied to the driver section; and an output control section that controls a voltage or a current of the test signal outputted from the driver section to the predetermined value, based on the supply current detected by the supply current detecting section.

Test apparatus and driver circuit

A first transform unit transforms clock change point information which indicates the change timing of a clock signal into information with respect to the frequency domain thereof so as to generate first clock change point frequency information. A digital filter performs filtering of the first clock change point frequency information so as to generate second clock change point frequency information. A second transform unit inverse-transforms the second clock change point frequency information into information with respect to the time domain so as to generate second clock change point information. A judgment unit evaluates a DUT based upon difference data between the change timing represented by the data change point information and the change timing represented by the second clock change point information in increments of phases.

A time measurement circuit measures the time difference between edges of a first signal and a second signal. A sampling circuit acquires the logical level of the first signal at a timing of the edge of the second signal. When a sampling circuit enters a metastable state, an output signal thereof transits with a long time scale. A transition time measurement circuit measures a transition time (settling time) of the output signal of the sampling circuit in the metastable state.

Time measurement circuit

A test apparatus that tests a device under test, including a signal input section that supplies a test signal to a device under test (DUT) and a judging section that judges acceptability of the DUT based on a response signal output by the DUT in response to the test signal. The signal input section includes an operation circuit that generates the test signal and a power supply stabilizing circuit provided in the same chip to stabilize power supply voltage supplied to the operation circuit. The power supply stabilizing circuit includes a high-speed compensating section compensating for a change in the power supply voltage supplied to the operation circuit, at a predetermined compensation speed, and as low-speed compensating section compensating for the change in the power supply voltage supplied to the operation circuit, at a predetermined compensation speed lower than that of the high-speed compensating section.

Power supply stabilizing circuit, electronic device and test apparatus

A test system that tests a plurality of chips under test formed on a wafer under test, the test system comprising a plurality of test substrates that are arranged in overlapping layers and that each have a plurality of test circuits, whose function is determined for each wafer, formed thereon; a plurality of connecting sections that electrically connect, to the chips under test, the test circuits formed on one of the test substrates; and a control apparatus that controls each of the test circuits. Each test substrate has test circuits, with a function predetermined for each substrate, formed thereon.

Test system and substrate unit for testing

A pattern generator generates test data to be transmitted. An encoding circuit generates amplitude data which represent a modulated signal waveform that corresponds to the test data. The amplitude data are generated in a parallel manner in the form of multiple amplitude data in increments of multiple sampling points set within a predetermined period for cycles of the predetermined period. A data rate setting unit receives the multiple amplitude data in increments of sampling points, latches the amplitude data at corresponding sampling timings, and sequentially outputs the amplitude data thus latched. A multi-level driver receives sequentially input amplitude data, and generates a test signal having a level that corresponds to the value of the amplitude data thus received.

Growing community of inventors

Tokyo, Japan

Toshiyuki Okayasu