Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Mitsubishi Electric Research Laboratories, Inc.

Toshiyuki Oishi

Yuji Abe

Katsuomi Shiozawa

Yasunori Tokuda

Naruhisa Miura

Hirokazu Sayama

Kazushige Kawasaki

Yukio Nishida

Kohei Sugihara

Hidekazu Oda

Koji Yamanaka

Kenichi Ohtsuka

Hiroshi Otsuka

Kyozo Kanamoto

Akihiko Furukawa

Yoichiro Tarui

Hitoshi Sakuma

Taisuke Furukawa

Toshihiko Shiga

Kenichi Kuroda

Yutaro Yamaguchi

Tetsuya Takami

Kazuyoshi Kojima

Yukihiko Wada

Akira Inoue

Koichi A Ono

Koon Hoo Teo

Chunjie Duan

Takaaki Murakami

Hiroshi Sugimoto

Tomohiro Sasagawa

Hiroshi Kurokawa

Junichi Horie

Tsuyoshi Horikawa

Yoshitsugu Yamamoto

Akihiro Suzuki

Takaaki Kawahara

Naohiko Fujino

Zempei Kawazu

Noboru Mikami

Takumi Nakahata

Hitoshi Wakata

Kenyu Haruta

Yosuke Suzuki

Mutsumi Tsuda

Hideki Yabe

Shinichi Miwa

Naoki Kosaka

Junji Tanimura

Takuma Nanjo

Kenji Yasumura

Teruhito Matsui

Kazuo Kuramoto

Shigemitsu Maruno

Muneyoshi Suita

Kouji Kise

Yoshio Saito

Peijie Feng

Nakayama Masatoshi

Tatsuo Omori

Keisuke Nanba

Akimasa Yuki

Tetsuo Makita

Hiroshi Kuroki

Tetsuo Ogama

Yasuji Matsui

A portion of an AlN spacer layer of a high electron mobility transistor (GaN HEMI) having a nitride semiconductor used therein is removed only in a region directly below a gate electrode and in a vicinity of the region, and a length of a portion where the AlN spacer layer is not present is sufficiently smaller than a distance between a source electrode and a drain electrode.

Transistor having nitride semiconductor used therein and method for manufacturing transistor having nitride semiconductor used therein

A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.

Transistor characteristic calculation apparatus using large signal equivalent circuit model

A device includes a source for transmitting an electronic charge through a conduction path; a drain for receiving the electronic charge; a stack for providing at least part of the conduction path; and a gate operatively connected to the stack for controlling a conduction of the electronic charge. The stack includes an insulator layer, an N-polar layer and a barrier layer selected such that, during an operation of the device, the conduction path formed in the N-polar layer includes a two-dimensional electron gas (2DEG) channel and an inversion carrier channel.

High electron mobility transistors with multiple channels

An isolation layer for suppressing a leakage current is provided at least between a channel layer and a buffer layer formed under the channel layer in the buffer layer.

Semiconductor device and manufacturing method thereof

The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero-junction field effect transistor provided with an AlGaN channel layer with a composition ratio of Al being x (0&#x3c;x&#x3c;1) formed on a substrate, an AlGaN barrier layer with a composition of Al being y (0&#x3c;y&#x2266;1) formed on the channel layer, and source/drain electrodes and a gate electrode formed on the barrier layer, wherein the composition ratio y is larger than the composition ratio x.

Nitride semiconductor heterojunction field effect transistor having wide band gap barrier layer that includes high concentration impurity region

A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, which is an antioxidant film for preventing oxidation of the Ta film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film as an antioxidant film is formed on the entire upper surface of the Ta film which forms the p electrode, to prevent oxidation of the Ta film. This inhibits the resistance between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the low-resistance p electrode.

Nitride semiconductor device including an electrode in ohmic contact with a P-type nitride semiconductor contact layer

A P-type electrode material is provided on a top surface of a P-type contact layer. The P-type electrode material is formed with an AuGa film, an Au film, a Pt film, and an Au film. The AuGa film is provided on the P-type contact layer. The Au film is provided on the AuGa film. The Pt film is provided on the Au film. The Au film is provided on the Pt film. With this, a nitride semiconductor device having a P-type electrode which can decrease a contact resistance between a P-type contact layer and the P-type electrode is obtained.

Nitride semiconductor device and method of manufacturing the same

A nitride semiconductor device includes an n-type GaN substrate with a semiconductor device formed thereon and an n-type electrode which is a metal electrode formed on the rear surface of the GaN substrate. A surface modified layer and a reaction layer are interposed between the GaN substrate and n-type electrode. The surface modified layer serves as a carrier supplying layer, and is formed by causing the rear surface of the GaN substrate to react with a Si-containing plasma to be modified. The reaction layer is generated by partially removing a deposited material deposited on the surface modified layer by cleaning to generate a deposited layer and then causing Ti contained in a first metal layer and the deposited layer to partially react by heat treatment.

Nitride semiconductor device and manufacturing method of the same

A nitride semiconductor device according to the present invention includes a P-type contact layer and a P-type electrode provided on the P-type contact layer. The P-type electrode includes a AuGa film provided on the P-type contact layer, a Au film provided on the AuGa film, a Pt filmprovided on the Au film, and a Au film provided on the Pt film. The ratio of the thickness of the AuGa film to the total thickness of the AuGa film and the Au film is not less than 12% but not more than 46%.

A method of manufacturing a semiconductor device provides a semiconductor device with a gallium-nitride-based semiconductor structure that allows long-term stable operation without degradation in device performance. After formation of an insulation film on a surface other than on a ridge surface, an oxygen-containing gas such as O, O, NO, NO, or NOis supplied to oxidize a p-type GaN contact layer from the surface and to thereby form an oxide film on the surface of the p-type GaN contact layer. Then, a p-type electrode that establishes contact with the p-type GaN contact layer is formed by evaporation or sputtering on the oxide film and on the insulation film. Heat treatment is subsequently performed at temperatures between 400 and 700&#xb0; C. in an atmosphere containing a nitrogen-containing gas such as Nor NHor an inert gas such as Ar or He.

Method of manufacturing semiconductor device including gallium-nitride semiconductor structure and a palladium contact

A nitride semiconductor device is manufactured by the step of forming a nitride semiconductor layer form on a GaN substrate main surface, the step of polishing a back surface of the GaN substrate formed with the above-mentioned nitride semiconductor layer, the step of dry etching the back surface of the GaN substrate subjected to the above-mentioned polishing by using a gas mixture of chlorine and oxygen, and the step of forming an n-type electrode on the back surface of the GaN substrate subjected to the above-mentioned dry etching.

Method of manufacturing nitride semiconductor device

A polysilicon nitride film is formed to cover a polysilicon gate. By heat treatment of the silicon nitride film in an oxygen atmosphere, a silicon oxinitride film is formed. By anisotropically etching the silicon oxinitride film and the silicon nitride film, a sidewall insulating film is formed. By epitaxial growth, selective silicon films of a prescribed film thickness are formed on source and drain regions. During this period, silicon islands are not deposited on the surface of sidewall insulating film. Consequently, a semiconductor device including a transistor of a superior electrical insulation can be obtained.

A field-effect transistor including a gate electrode, silicon layers, and source and drain regions at a surface of a silicon substrate. Sidewall insulating films on the opposite side surfaces of the gate electrode are located between the gate electrode and the silicon layers and contain respective voids.

Semiconductor device

A method of producing a semiconductor device includes forming a gate electrode on a channel region on a surface of a semiconductor region of a semiconductor substrate, the channel region having a depth in the semiconductor substrate; forming a first pair of side wall spacers on opposite sides of the gate electrode; forming elevated semiconductor layers, each elevated semiconductor layer being elevated relative to the channel region, on regions outside of the pair of side wall spacers and in which source and drain regions of a first conductivity type are to be formed; removing the pair of first side wall spacers; and forming a pair of pocket injection regions of a second conductivity type by introducing, after the side wall spacers are removed, a dopant impurity producing the second conductivity type deeper in the semiconductor substrate than a region where the side wall spacers were formed, the pair of pocket injection regions respectively covering only a neighborhood of respective side surface parts of the channel region, where the source and drain regions are to be formed, forming respective pn junctions only between the neighborhood of the side surface parts and the pocket injection regions.

Method of making field effect transistor in which the increase of parasitic capacitance is restrained by scale reduction

Source and drain regions include regions of an epitaxial silicon film on the surface of the substrate and regions in the substrate. The depth of junctions of the source and drain regions is identical to or shallower than the depth of junctions of extension regions. As a result, even if the thickness of the side wall layer is reduced, since the depletion layer of the extension regions with lower impurity concentration compared with the source and drain regions is predominant, the short channel effect has a smaller effect.

Semiconductor device with sidewall spacers and elevated source/drain region

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Tokyo, Japan

Toshiyuki Oishi