Kabushiki Kaisha Toshiba

Toshiyo Motozima

Jiro Ohshima

Shin-ichi Taka

Hiroshi Naruse

Jiro Oshima

In a semiconductor device, the polysilicon resistor or electrode formed of a polysilicon film has a columnar crystalline orientation vertical to the surface of the semiconductor substrate. Thus, the variation in grain size due to the subsequent heat treatment is small, and therefore, the polysilicon resistor or electrode has a high uniformity of resistance value. In addition, since the polysilicon film is formed in the groove in the insulating film formed on the semiconductor substrate, a polysilicon pattern surface which is flush with the surface of the insulating film can be obtained. Thus, unevenness does not occur on the surface of a passivation CVD film coated in the subsequent step, and metal wires formed thereon are not cut.

Method of manufacturing polycrystalline silicon having columnar

According to the method of manufacturing a semiconductor device of the present invention, an insulation film is formed on a silicon substrate, and a resist film having a predetermined pattern is formed on the insulation film, followed by forming an opening on the insulation film with the resist film performing as a mask. Then, an impurity having conductivity are implanted into said silicon substrate with the resist film performing as a mask and silicon ions are implanted into the silicon substrate with the resist film performing as a mask. After that, the resist film is removed. Further, a refractory metal film which covers at least the opening is formed. Moveover, a diffusion layer which causes electrical activation of the impurity having conductivity is formed by annealing, followed by formation a silicide layer at where the surfaces of the silicon substrate and the metal film meet.

Method of manufacturing a semiconductor device having a silicide layer

In the invention, the width of the emitter contact layer is determined in accordance with the width of a first side wall, and the junction distance between a base contact layer and the emitter contact layer is determined in accordance with the width of a second side wall. The junction distance between the emitter contact layer and the base contact layer can be decreased, no extra high-temperature annealing such as thermal oxidation is needed, and the diffusion profile can be controlled to be shallow.

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Yokohama, Japan

Toshiyo Motozima