Nec Corporation

Takasago International Corporation

Nippon Telegraph and Telephone Corporation

Ando Electric Company

Fujitsu Microelectronics Limited

The Mennen Company

Kohjin Life Sciences Co., Ltd.

Toshiya Sato

Kenya Ishida

Hamako Hata

Kazuhisa Ninomiya

Akira Shimizu

Morton L Barr

Tsuneo Horiguchi

Kiyohito Sawano

Augustinus G Van Loveren

Hajime Hiroi

Mikio Maeda

Robert Suffis

Katsuto Tanahashi

Tatsuyuki Fujita

Satoko Tsukada

Hirohisa Ooishi

A combinatorial optimization problem processing device is for associating a combinatorial optimization problem having N elements with an Ising model to process the combinatorial optimization problem. The combinatorial optimization problem processing device includes: a 1&#xd7;2 Mach-Zehnder optical modulator that receives a polarized clock pulse train; an optical interference circuit that receives polarized clock pulse trains that were modulated by the Mach-Zehnder optical modulator; an optical coupler that couples output of the optical interference circuit with an initialization optical pulse train that creates a neutral state with respect to interactions between the elements; and a modulation signal generator that performs waveform shaping on an electrical signal obtained by photoelectrically converting an output signal of the optical coupler, generates a modulation signal for the Mach-Zehnder optical modulator, and externally outputs a monitor signal that represents a solution to the optimization problem. The optical interference circuit repeatedly allows a predetermined interaction in the Ising model to occur from the neutral state at a period corresponding to the N pulses of the polarized clock pulse train.

Combinatorial optimization problem processor and method

A classification apparatus for the semiconductor substrate is provided with a bow measuring section which accepts silicon substrates and measures respective bows thereof. The classification apparatus is also provided with a bow judging section which, based on one or more standard value(s) set in advance, checks a measurement result by the bow measuring section against the standard value(s). The bow judging section judges to which of ranges defined based on the standard value(s) of the bow the measurement result by the bow measuring section belongs. Further, the classification apparatus is provided with a sorting section which accepts the silicon substrate having been measured by the bow measuring section and sorts the accepted silicon substrates based on the judgment results by the bow judging section. In other words, silicon substrates are grouped according to the bows by the sorting section. Then, respective silicon substrates are discharged in a grouped state.

Classification apparatus for semiconductor substrate, classification method of semiconductor substrate, and manufacturing method of semiconductor device

An electrically writable nonvolatile semiconductor memory device capable of writing data to any desired threshold value accurately without resorting to a write confirming operation is disclosed. The memory device senses a current flowing through a memory cell transistor while effecting a writing operation. When the current reaches a preselected value, the memory device stops the writing operation. A relation between a desired threshold voltage and the current to flow through the memory cell transistor during wiring is determined beforehand. This eliminates the need for the confirmation of the threshold voltage relying on a reading operation, and allows a desired threshold voltage to be set rapidly and accurately.

Electrically writable nonvolatile semiconductor memory device

In a semiconductor device having 'N' input terminals, a high voltage for a mode switching is applied to a first input terminal, and mode setting information is supplied to the other input terminals. A latch circuit holds the mode setting information supplied during a predetermined period of time starting from application of the high voltage to the first input terminal, during a period of time in which the high voltage continues to be supplied to the first input terminal. Thus, a test is performed on the basis of the mode switching instruction held in the latch circuit and data applied to the other input terminals. On the other hand, if the high voltage is disconnected, the latch circuit is reset.

Semiconductor device having a test mode setting circuit

In a nonvolatile semiconductor memory device, a nonvolatile counter is provided to store a number of erasing operations. A time period of a writing operation upon a memory cell is changed in accordance with the number of erasing operations. Also, a time period of an erasing operation upon memory cells is changed in accordance with the number of erasing operations.

Nonvolatile semiconductor memory device having variable writing and

The non-volatile semiconductor memory disclosed includes an X-decoder and word line potential supply circuits, and a current setting/holding circuit. The X-decoder and the word line potential supply circuits set all word lines ground potential in the flash erasing operation, to a predetermined first over-erasing judgment reference potential in an 'on' cell detecting operation, and to a predetermined second over-erasing judgment reference potential for judgment of over-erasing deeper than the first over-erasing judgment reference potential and, in an 'on' cell specifying operation, set predetermined selected word lines to the first over-erasing judgment reference potential while setting other word lines than the selected word line to the second over-erasing judgment reference potential. The current setting/holding circuit sets the reference current in an 'on' cell specifying reference current setting operation such that the result of the check by a sense amplifier is 'on'. It is possible to eliminate the possibility of generation of a memory cell transistor in a non-erased state, thus ensuring quick operation.

Non-volatile semiconductor memory and data erasing method for the same

An electrically erasable and programmable read only memory device enters an automatic erasing mode of operation, and repeats short erasing operation followed by confirmation of proper erased state in the automatic erasing mode, wherein the memory cell array is inspected to see whether or not each memory cell not only enters the erased state but also remains in enhancement mode so that the memory cell array is exactly programmed in a programming mode of operation.

Electrically erasable and programmable read only memory device equipped

Disclosed herein is a flash type EEPROM which includes a first memory cell array having a plurality of first memory cells, a second memory array having a plurality of memory cells which are smaller in number than the first memory cells, a voltage generator operatively generating an erasing voltage in an erase operation mode, a first transfer gate circuit operatively transferring the erasing voltage to each of the first and a second transfer gate circuit operatively transferring the erasing voltage to each of the second memory cells, the first transfer gate circuit having a current driving capability larger than the current driving capability of the second transfer gate circuit.

Flash EEPROM having memory cell arrays supplied respectively with

An optical pulse tester capable of displaying Raman scattered light is disclosed. An optical pulse with the specified wavelength is injected into an optical fiber to be measured via a directional coupler and an optical demultiplexer/multiplexer. The demultiplexer/multiplexer demultiplexes returning light from the optical fiber into Raman scattered light different from the optical pulse in wavelength. The directional coupler divides returning light from the optical fiber into Fresnel reflection light and Rayleigh scattered light with the specified wavelength. The switcher supplies the Rayleigh scattered light to a display In the case of long distance measurement or precise loss measurement of the optical fiber. Therefore, the display displays the characteristic waveform of the optical fiber with the Rayleigh scattered light. In contrast, the switcher supplies the Raman scattered light to the display in the case of the measurement of the near-end part of the optical fiber or the connecting point between optical fibers without a dead area. Therefore, the display displays the characteristic waveform of the optical fiber with the Raman scattered light.

Optical pulse tester capable of displaying Raman or Rayleigh scattered

Described is a fragrancing composition having fragrancing components that are not activated until, e.g., application to the skin of a human. The composition is alkaline or (if anhydrous) capable of producing an alkaline pH when in contact with water, prior to application, and includes (1) a vehicle for application of the composition, and (2) at least one potential fragrance that is at least one compound having little or no odor in the alkaline composition but which, e.g., is hydrolyzed in a lower pH environment to produce compounds having a relatively strong aroma. Upon application of the alkaline composition to the skin surface, the strong buffering capacity of the skin (the surface of which has a normal pH of 5.5-7.0) neutralizes alkalinity of the composition (lowers pH) so as to restore normal skin surface pH; the potential fragrance is then hydrolyzed at the lower pH to release the compound having relatively strong aroma. The potential fragrance can be incorporated as a component of a transparent (clear) deodorant stick composition for application to human axillary regions, the fragrance being released after application to the body.

Composition containing body activated fragrance for contacting the skin

A topical composition for treating or preventing acne vulgaris which comprises at least one saturated or unsaturated chain alcohol having 18 carbon atoms represented by formula (1): ##STR1## wherein a dotted line represents either the presence or the absence of a double bond as an active ingredient, makes it possible to inhibit proliferation of Propionibacterium acnes, which causes acne vulgaris, or kill the bacterium to effectively treat or prevent acne vulgaris. The compound represented by formula (1) can be easily synthesized and has an extremely low toxicity. Furthermore, it exerts an excellent antibacterial effect on Propionibacterium acnes even when used at a relatively low concentration. Thus it can be used only in a small amount , which ensures a high safety.

Topical composition for preventing or treating acne vulgaris

A semiconductor memory device uses a memory cell array having of a plurality of cell array blocks, a redundancy cell array as a replacement for a cell array block containing a faulty memory cell, a replacement-information memory circuit for holding faulty-cell detection information and discrimination information of a cell array block containing a faulty cell in a plurality of memory transistors each, in normal mode, with source and control gate electrodes kept at ground potential and a drain electrode kept at a specified voltage of lower potential than the supply voltage. Each is forced into depletion or enhancement mode depending on the accumulated charge on the floating gate. The memory also includes a redundancy selector for outputting the redundancy signal which goes to active level by the decision based on an information held in this replacement-information memory circuit that a cell array block containing a faulty cell has been selected.

Semiconductor memory device

A data logging apparatus for a device function tester comprises a first shift circuit (1) supplied with an output signal of the tester and a strobe signal for shifting the output of the tester by n rates under the timing of a basic clock (T.sub.0), a second shift circuit (2) for shifting the timing of the basic clock (T.sub.0) by n rates, a write pulse generating circuit (3) supplied with the output signal of the shift circuit (2), a third shift circuit (4) supplied with a memory address signal for shifting it by n rates under the timing of the basic clock (T.sub.0), a fourth shift circuit (5) for shifting a pattern address signal by n rates under the timing of the basic clock (T.sub.0), a first memory (6) supplied with the output signal of the first shift circuit (1) and the output signal of the third shift circuit (1) for storing the result of the test shifted by n rates in response to a write command signal, and a second memory ( 7) supplied with the output of the fourth shift circuit (5) and the output of the third shift circuit (4) for storing the pattern address shifted by n rates in response to the write command signal. Data logging can be accomplished without being affected by variable time intervals of write enable strobe pulses.

Data logging apparatus with memory and pattern testing device

When an electrically erasable and program read only memory device enters an erasing mode of operation, electrons are evacuated from floating gate electrodes of the floating gate type field effect transistors serving as memory cells, and the evacuation is continued over a time period instructed from an internal memory circuit so that the memory cells are prevented from depletion mode due to excess evacuation as well as from non-erased state due to insufficient evacuation.

Growing community of inventors

Tokyo, Japan

Toshiya Sato