Samsung Electronics Co., Ltd.

Toshiro Nakanishi

Chanjin Park

Kihyun Hwang

Sunghoi Hur

Kwangmin Park

Hanmei Choi

Wansik Hwang

Kwang Soo Seol

Juyul Lee

Jin Soak Kim

Suhwan Kim

Ki-Hyun Hwang

Siyoung Choi

Donghwan Kim

Bonyoung Koo

Gab-Jin Nam

Taehyun An

Sungkweon Baek

Gabjin Nam

Yubin Kim

Eunae Chung

Dongwoo Kim

Jong-Ho Lee

Dong Hwan Kim

Jae-young Ahn

Jung-dal Choi

Kwang-Soo Seol

Bio Kim

Jaeyoung Ahn

Dongchul Yoo

Eun-ae Chung

Seung-hyun Lim

SeungHyun Lim

Su Hwan Kim

Choong-Man Lee

Dong-kyu Lee

Jin-Tae Noh

Chang-Woo Sun

Bi-O Kim

Tae-Hyun An

Guangfan Jiao

Ju-Yul Lee

Sung Kweon Baek

Eun Ae Chung

Yu-bin Kim

Gab Jin Nam

Tae Hyun An

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

Three-dimensional semiconductor memory devices and methods of fabricating the same

A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.

Static random access memory (SRAM) cells including vertical channel transistors and methods of forming the same

Static random access memory (SRAM) cells including vertical channel transistors

A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.

Semiconductor device including FinFETs having different gate structures and method of manufacturing the semiconductor device

There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric layer for gate insulation on the active region; forming a curing layer with a material containing germanium (Ge) on the dielectric layer; heat-treating the curing layer; and removing the curing layer. The germanium-containing material may be silicon germanium (SiGe) or germanium (Ge).

Method of manufacturing semiconductor device

A semiconductor device includes a substrate including an NMOS region, a fin active region protruding from the substrate in the NMOS region, the fin active region including an upper surface and a sidewall, a gate dielectric layer on the upper surface and the sidewall of the fin active region, a first metal gate electrode on the gate dielectric layer, the first metal gate electrode having a first thickness at the upper surface of the fin active region and a second thickness at the sidewall of the fin active region, and a second metal gate electrode on the first metal gate electrode, the second metal gate electrode having a third thickness at the upper surface of the fin active region and a fourth thickness at the sidewall of the fin active region, wherein the third thickness is less than the fourth thickness.

Semiconductor device having tri-gate transistor and method of manufacturing the same

Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.

Vertical memory devices and methods of manufacturing the same

A method for fabricating a cell string includes forming an interlayer dielectric layer, a sacrificial layer, and a semiconductor pattern on a semiconductor substrate, such that the interlayer dielectric layer and the sacrificial layer are formed in a first direction parallel with the semiconductor substrate, and such that the semiconductor pattern is formed in a second direction perpendicular to the semiconductor substrate, forming an opening by patterning the interlayer dielectric layer and the sacrificial layer, filling the opening with a metal, and annealing the semiconductor pattern having the opening filled with the metal.

Methods for fabricating a cell string and a non-volatile memory device including the cell string

Provided are three-dimensional semiconductor devices. The device includes conductive patterns stacked on a substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern includes a first doped region disposed adjacent to at least one of the conductive patterns, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

Three-dimensional semiconductor memory devices

A non-volatile memory device includes: word line disposed on a substrate; an active region crossing over the word line; and a charge trap layer that is between the word line and the active region.

Non-volatile semiconductor memory devices having charge trap layers between word lines and active regions thereof

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Seongnam-si, South Korea

Toshiro Nakanishi