Other

Hitachi, Ltd.

Hitachi Ulsi Engineering Corp.

Toshiro Aoto

Koichiro Ishibashi

Sadayuki Morita

Shuji Ikeda

Toshiaki Yamanaka

Satoshi Meguro

Naotaka Hashimoto

Masayuki Kojima

Atsuyoshi Koike

Katsuro Sasaki

Kazuyuki Suko

Kyoichiro Asayama

Fumiyuki Kanai

Kunihiro Komiyaji

Yasuo Kiguchi

Eri Fujita

A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.

Semiconductor integrated circuit device

Semiconductor memory device having driver and load MISFETs and capacitor elements

A semiconductor static memory device, which has an increased storage capacity without imposing an increased access time, includes first, second and third metallic layers. To begin, word lines for the transfer MOSFETS are formed of the same polysilicon layer used to form the gate electrodes of the transfer MOSFETs of the memory device. A metallic layer of the first layer is used for local word lines, with the polysilicon word lines and local word lines being connected at their ends or inside of cell arrays. A metallic layer of the second layer is used for bit layers, and a metallic layer of the third layer is used for main word lines. Consequently, the word lines have a decreased time constant, allowing fast memory access. Each of sense amplifiers used in the memory device are formed with MOSFETs, which are disposed divisionally in adjacent locations. Preferably the gate electrodes of the divided MOSFETs are located symmetrically. In this case, the offset voltage of the sense amplifiers decreases significantly.

Semiconductor memory device having a large storage capacity and a high

Semiconductor memory device

Growing community of inventors

Musashimurayama, Japan

Toshiro Aoto