Denso Corporation

Nippondenso Co., Ltd.

Hitachi, Ltd.

Denso Corpora Tion

Toshio Sakakibara

Takayuki Sugisaka

Shoji Miura

Makio Iida

Tsuyoshi Yamamoto

Atsuo Watanabe

Hitoshi Yamaguchi

Toshiyuki Morishita

Hiroki Nakamura

Tetsuo Fujii

Eiichi Okuno

Hiroyuki Ban

Yasushi Urakami

Shoichi Yamauchi

Mitsuhiro Saitou

Satoshi Shiraki

Jun Sakakibara

Nobuyoshi Sakakibara

Takumi Shibata

Takasumi Ohyanagi

Makoto Ohkawa

Kunihiro Onoda

Yasuaki Tsuzuki

Ichiro Ito

Tomio Yamamoto

Atsumi Takahashi

Akito Fukui

Hiroshi Fujimoto

Hiroshi Maeda

Hiroshi Imai

Shoji Mizuno

Masami Yamaoka

Rajesh Kumar Malhan

Hiroshi Iwasaki

Akihiko Teshigahara

Akiyoshi Asai

Yoshiaki Nakayama

Yasuhiro Kitamura

Tadashi Shibata

Hiroyasu Itou

Nobuhiro Tsuji

Atsushi Komura

Kenji Kohno

Yoshinori Otsuka

Tadashi Suzuki

Osamu Ishihara

Akitaka Murata

Ryuichirou Abe

Takasumi Ooyanagi

A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.

SIC semiconductor device and method for manufacturing the same

A silicon carbide semiconductor device includes a semiconductor element disposed in a semiconductor substrate having a first conductive type silicon carbide layer and a silicon substrate. The device includes: a trench on the silicon carbide layer to reach the silicon substrate; and a conductive layer in the trench between the silicon carbide layer and the silicon substrate to connect to both of them. The semiconductor element is a vertical type semiconductor element so that current flows on both of a top surface portion and a backside surface portion of the semiconductor substrate. The current flows through the conductive layer.

Silicon carbide semiconductor device

A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.

Semiconductor device

A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.

Semiconductor device including a vertical field effect transistor, having trenches, and a diode

A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.

Power MOS transistor for absorbing surge current

An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.

Method of etching metallic thin film on thin film resistor

In a semiconductor device, a p-type base region is provided in an n -type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n -type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n -type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n -type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

Method of manufacturing semiconductor device having trench filled up with gate electrode

Semiconductor device having trench filled up with gate electrode

A trench is formed in a silicon substrate, and an epitaxial film is formed on the substrate and in the trench. After a part of the epitaxial film formed around an opening portion of the trench is etched, another epitaxial film is formed on the substrate and in the trench. Accordingly, the trench can be filled with the epitaxial films completely. Then, the surface of the substrate is flattened.

Method for manufacturing semiconductor substrate having an epitaxial film in the trench

A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that an opening width thereof is wider than that of the trench. After that, an inner surface of the trench is smoothed by thermal treatment around at 1000&deg; C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished, whereby a semiconductor substrate for forming a semiconductor device is obtained.

Method of improving epitaxially-filled trench by smoothing trench prior to filling

An island region surrounded by a trench is provided in an SOI substrate. The island region is further surrounded by a buffer region with a buffer region contact layer. In the island region, a source region is annularly provided around a drain region, and source and drain electrodes are respectively provided on the source and the drain regions. An annular auxiliary electrode is formed with the source electrode to extend over the trench. Accordingly, a voltage applied to the source electrode can be applied to the auxiliary electrode, so that electric field concentration between the buffer region and the source electrode is relaxed.

Semiconductor apparatus having high withstand voltage

A semiconductor device including a semiconductor substrate having a main surface. An insulating film is formed on the main surface of the semiconductor substrate. A semiconductor layer is placed on the insulating film. Side insulating regions extending from a surface of the semiconductor layer to the insulating film divide the semiconductor layer into element regions. The element regions are isolated from each other by the side insulating regions and the insulating film. The semiconductor substrate has a resistivity of 1.5 .OMEGA.cm or lower. A voltage at the semiconductor substrate is set to a given voltage.

Design for a semiconductor device having elements isolated by insulating

A semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. A PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14. This mitigates electrostatic focusing in the vicinity of the corner parts between the sides of the base region 5 and the bottom thereof, restraining the avalanche breakdown there and improving the withstand voltage there.

High withstand voltage type semiconductor device having an isolation

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Nishio, Japan

Toshio Sakakibara