Hitachi, Ltd.

Toshinari Takada

Haruo Akahoshi

Akio Takahashi

Akira Nagai

Toshikazu Narahara

Motoyo Wajima

Takeyuki Itabashi

Shin Nishimura

Shigeo Amagi

Masahiro Suzuki

Shiro Kobayashi

Yoshihiro Suzuki

Masashi Miyazaki

Kiyonori Kogawa

Kanji Yamamoto

Rituji Toba

Tomoyuki Miyazaki

Satoru Amo

Fujiko Yutani

A wiring pattern forming method in which side etch of a wiring pattern at the time of etching the substrate copper foil of a copper plating pattern is reduced to hold down an increase in line resistance, the wiring pattern forming method including the steps of: providing a plating resist pattern of which open area comprises a wiring pattern on the surface of a copper-clad laminate which is obtained by providing a copper foil on an insulating substrate; plating such open area with copper to form a copper plating pattern; then plating a crevice between the copper plating pattern and the plating resist pattern with a solder film by alternately repeating application of a current for a predetermined time period and suspension of the current application for a predetermined time period; and etching away the copper foil by using the solder film as an etching resist to form the wiring pattern.

Method for forming wiring pattern

A process is provided for the formation of a conductive circuit pattern on a base metal formed on a substrate. On the base metal, a plating resist is first provided in a pattern corresponding to the circuit to be formed and a circuit pattern is then formed by plating. The plating resist is treated with a stripper and then with a stripping residue remover to cut off chemical bonds in the resist by a dehydrating decomposition reaction. The base metal is treated with an etchant for the base metal, whereby any resist residue still remaining after the treatment with the stripping residue remover is removed and the base metal are etched at areas which were covered by the plating resist.

Process for the formation of a conductive circuit pattern

A circuit board, which comprises an insulating substrate, a copper wiring having a coarsely roughened surface provided on the insulating substrate, and a copper oxide-reduced layer provided on the coarsely roughened surface of the copper wiring and formed by reduction of copper oxide and electroless plating, the copper oxide-reduced layer having a finely roughed surface and having a deposited layer of at least one of nickel and cobalt, where the copper oxide-reduced layer having a deposited layer of at least one of nickel and cobalt on the surface is roughened in a range of 0.05 to 5 .mu.m in terms of a maximum vertical distance between the top of convex parts and the bottom of concave parts of the copper oxide-reduced layer per .mu.m of the longitudinal distance of the copper oxide-reduced layer, and at least one of nickel and cobalt is deposited in an amount of 5.times.10.sup.-7 to 1.times.10.sup.-4 g/cm.sup.2 on the copper oxide-reduced layer, has a high adhesiveness to an insulating resin.

Circuit board and process for producing the same

Growing community of inventors

Hadano, Japan

Toshinari Takada