Intel Corporation

Toshimi Kohmura

Charan K Gurumurthy

Munehiro Toyama

David Gregory Figueroa

Michael Walk

Hideki Goto

Joan K Vrtis

Aaron Dean Hale

An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth such that the device surface is approximately planar with the substrate surface. The first device is attached to a second device via bumps on the second device.

Embedding device in substrate cavity

Vias and conductive pads configured and coupled in a manner to reduce delamination are described herein. The via and the conductive pads may be located in a substrate such as a carrier substrate, a die, or a printed circuit board.

Delamination reduction between vias and conductive pads

An electronic package ( , FIG. ) includes one or more capacitors ( ) embedded within one or more layers ( ) of the package. The embedded capacitors are discrete devices, such as integrated circuit capacitors (FIGS. ) or ceramic capacitors. During the package build-up process, the capacitors are mounted ( , FIG. ) to a package layer, and a non-conductive layer is applied ( ) over the capacitors. When the build-up process is completed, the capacitor's terminals ( , FIG. ) are electrically connected to the top surface of the package. The embedded capacitor structure can be used in an integrated circuit package ( , FIG. ), an interposer ( ), and/or a printed circuit board ( ).

Electronic package having embedded capacitors and method of fabrication therefor

Growing community of inventors

Tsuchiura, Japan

Toshimi Kohmura