Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Toshiki Hisada

Dai Nakamura

Takatoshi Minamoto

Noboru Shibata

Katsuaki Isobe

Masaru Koyanagi

Hiroyuki Koinuma

Katsuki Matsudera

Kazuhide Yoneya

Hiromitsu Mashita

Natsuki Kushiyama

Takahiko Hara

Kaoru Nakagawa

Nobuaki Okada

Mitsuhiro Noguchi

Tsuneo Inaba

Tohru Ozaki

Kazushige Kanda

Toshifumi Hashimoto

Yoshiko Kato

Shigeru Ishibashi

Takafumi Taguchi

Takayuki Toba

Yuya Suzuki

Tohru Kimura

Yoshikazu Hosomura

Manami Kudou

Yutaka Shirai

A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.

Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate

A semiconductor storage device includes first and second chips. The first chip includes a first semiconductor substrate, first conductive layers arranged in a first direction and extending in a second direction, a semiconductor column extending in the first direction and facing the first conductive layers, a first charge storage film formed between the first conductive layers and the semiconductor column, a plurality of first transistors on the first semiconductor substrate, and first bonding electrodes electrically connected to a portion of the plurality of first transistors. The second chip includes a second semiconductor substrate, a plurality of second transistors on the second semiconductor substrate, and second bonding electrodes electrically connected to a portion of the plurality of second transistors, and bonded to the first bonding electrodes. A thickness of the second semiconductor substrate in the first direction is smaller than a thickness of the first semiconductor substrate in the first direction.

Semiconductor storage device with transistors of peripheral circuits on two chips

A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M&#x3c;N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

Semiconductor memory device capable of reducing chip size

A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M&#x3c;N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffuse layers.

A semiconductor memory device includes a first block that includes a first set of word lines, a second block that includes a second set of word lines and is adjacent to the first block in a first direction, a first transistor group adjacent to the first and second blocks in a second direction crossing the first direction, and a second transistor group adjacent to the first transistor group in the second direction. Each of the word lines in the first set is electrically connected to a transistor in the first transistor group, and each of the word lines in the second set is electrically connected to a transistor in the first transistor group.

Semiconductor memory device

Growing community of inventors

Yokohama, Japan

Toshiki Hisada