Hitachi, Ltd.

Japan Science and Technology Agency

Director-general of the Agency of Industrial Science and Technology

Toshikazu Shimada

Kiyoo Itoh

Kazuo Nakazato

Hiroshi Mizuta

Hideo Sunami

Yoshifumi Katayama

Haruo Itoh

Toshiyuki Mine

Tetsuhiko Takahashi

Eiichi Maruyama

Ken Yamaguchi

Toshihiko Sato

Tatsuya Teshima

Minoru Yoshida

Hiroshi Takeuchi

Kenji Maio

Masahiko Ando

Shunri Oda

Nobuyoshi Koshida

Hirokazu Matsubara

Akitoshi Ishizaka

Haroon Ahmed

Sunao Matsubara

Shin-ichi Muramatsu

Nobuo Nakamura

Natsuki Yokoyama

Hideaki Yamamoto

Akio Nishida

Tadaaki Hirai

Takashi Kajimura

Yasuhiro Shiraki

Michiharu Nakamura

Kenichi Okajima

Kiyokazu Nakagawa

Masakazu Ichikawa

Jun-ichi Umeda

Yoshimasa Murayama

Shinya Yamaguchi

Shigeo Yamashita

Hideji Fujii

Akira Shintani

Makoto Fujikura

Kiichi F Komatsubara

Haruo Itho

Hirosh Takeuch

Shinichi Muramatsu

Hiroyuki Etoh

Masatoshi Shiiki

Seijiro Furukawa

An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (), and a floating gate layer () having two stable deflection states in the cavity (), the state stabilized by deflecting toward the channel side of transistor, and the state stabilized by deflecting toward the gate () side, writing and reading of information can be made by changing the stable deflection state of the floating gate layer () by Coulomb interactive force between the electrons (or positive holes) accumulated in the floating gate layer () and external electric field, and by reading the channel current change based on the state of the floating gate layer ().

Information storage element, manufacturing method thereof, and memory array

A controllable conduction device in the form of a transistor comprises source and drain regionsbetween which extends a conduction path P for charge carriers, a gatefor controlling charge carrier flow along the conduction path and a multiple layer structureproviding a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Controllable conduction device with electrostatic barrier

The present invention provides a solid state light-emissive display apparatus of high brightness and efficiency, high reliability, and of thin type, and method of manufacturing the same at low cost. Said apparatus has the luminous thin film made up by laminating or mixing crystal fine particle coated with insulator () of nm size and fluorescent fine particles () of nm size, and the lower electrode and the transparent upper electrode sandwiching said luminous thin film, wherein the electrons injected from said lower electrode are accelerated in the crystal fine particle coated with insulator layer () not being scattered by phonons to become high energy ballistic electrons, and form excitons () by colliding excitation of fluorescent fine particles. Since said fluorescent fine particles are of nm size, the exciton concentration is high, and luminescence intensity by extinction of excitons is also high.

Solid-state self-emission display and its production method

Semiconductor memory device and manufacturing method

A memory device includes a memory node ( ) to which charge is written through a tunnel barrier configuration ( ) from a control electrode ( ). The stored charge effects the conductivity of a source/drain path ( ) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers ( ) of polysilicon of 3 nm thickness and layers ( ) of Si N of 1 nm thickness, overlying polycrystalline layer of silicon ( ) which forms the memory node. Alternative barrier configurations ( ) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands ( ), which act as the memory node, distributed in an electrically insulating matrix.

Memory device

Semiconductor memory device and manufacturing method thereof

A controllable conduction device in the form of a transistor comprises source and drain regions,between which extends a conduction path P for charge carriers, a gate,for controlling charge carrier flow along the conduction path and a multiple layer structure,providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Controllable conduction device

A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si.sub.3 N.sub.4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

Memory device with improved charge storage barrier structure

By i) forming a layered structure of an undoped single crystalline Si layer and single crystalline Si.sub.0.8 Ge.sub.0.2 mixed crystal layer on an n-Si(100) substrate, a second undoped single crystalline Si layer on it, and a p type hydrogenated amorphous Si.sub.1-B C.sub.B layer on it, iii) mounting an n-Si.sub.0.55 Ge.sub.0.40 C.sub.0.05 layer on an n-Si(100) substrate and forming a layered structure of an undoped single crystalline Si.sub.0.55 Ge.sub.0.40 C.sub.0.05 layer and Si.sub.0.8 Ge.sub.0.2 layer, an undoped single crystalline Si.sub.0.55 Ge.sub.0.40 C.sub.0.05 layer, and a p-Si.sub.0.55 Ge.sub.0.40 C.sub.0.05 layer sequentially on it or iv) mounting an n type single crystalline Si layer on an n-Si(100) substrate and forming a layered structure of an undoped single crystalline Si layer and Si.sub.0.8 Ge.sub.0.1 Sn.sub.0.1 layer, an undoped single crystalline Si layer, and a p type single crystalline Si layer sequentially on it, a semiconductor optical device is obtained.

Semiconductor optical device, manufacturing method for the same, and

An optical nanodisplacement producing apparatus is realized by employing an optical parametric oscillator of which cavity length is varied in correspondence with a wavelength or the intensity of the output light signal to achieve a fine-displacement producing mechanism. An optical nanodisplacement producing apparatus having high resolution less than 0.1 nm and a highly stable characteristic is realized as a very fine pattern forming/monitoring apparatus.

Nanodisplacement producing apparatus

A radiation detector for use on X-ray CT scanner with a plurality of elements arrayed to form a detector block, which is structured that a plurality of thin-film photodiodes consisting of amorphous silicon each are formed on the back of a scintillator block having a width to cover the plurality of elements, a platelike supporting member provided with signal lines on the back is bonded to cover the photodiodes, the photodiodes and the signal lines are connected together through wire bonding, the scintillator block is divided into each element across separators on the supporting member.

Radiation detector and manufacturing process thereof

This invention relates to a multi-element type radiation detector for an X-ray CT scanner system wherein a plurality of scintillator blocks that are isolated either optically or radiation-wise from one another are arranged integrally, and a photo-diode consisting of an amorphous silicon layer for converting the emission of each scintillator is formed on the surface of each scintillator block by thin film technique.

Multi-element type radiation detector

In a radiation detector having a scintillator and a photodiode in combination, an amorphous silicon diode of a refractive index of 3.5 or below is used for a photodector to have a decreased junction capacitance. This shifts the spectral sensitivity characteristic of the photodetector toward the short wavelength side, thus providing a low-noise, high-sensitivity radiation detector matched well with the emission spectrum of the scintillator.

Radiation detector

Growing community of inventors

Tokyo, Japan

Toshikazu Shimada