Nec Corporation

Nippon Electric Co., Ltd.

Toshihide Tsuboi

Tomokazu Kai

Norio Funahashi

An improved layout of transistors near LCD drive terminals in a CMOS semiconductor device to reduce a chip size without damaging resistances against electrostatic destruction and latch-up. MOSFETs whose sources are connected to neither an electric source nor a ground are selectively arranged between two protective diffusion layers having different polarities, connected to a terminal.

CMOS semiconductor device with improved layout of transistors near LCD

A semiconductor device includes a CMOSFET, including n-channel and p-channel MOSFETs. A terminal is connected to a node connecting the drains of the MOSFETs. A pull-up or pull-down resistor is connected between the terminal and a power source potential. The pull-up or pull-down resistor is composed of two serially-connected resistances. One of the two serially connected resistances is connected to the terminal and is formed of a resistance material that does not form a pn junction with a semiconductor substrate, and the other of the two resistances is formed of a diffusion layer of conduction type that forms a pn junction with the semiconductor substrate.

Semiconductor device having pull-up or pull-down resistance

An information processing device according to the present invention includes a logical circuit which outputs a signal for indicating that an error correction has been conducted on a data, when an error check and correction (ECC) circuit detects and corrects an error of data at the time of reading data from a memory cell array of an electrically erasable programmable ROM (EEPROM). In the information processing device of the present invention, while the EEPROM outputs the correct data by means of the ECC circuit, it can be known whether there exists an error even in a part of the cells in the EEPROM, so that it is possible to alter an address of a memory cell containing an erroneous bit in the EEPROM or to change the EEPROM itself before malfunction occurs in the information processing device having the EEPROM due to a breakdown of the memory cells in the EEPROM.

Information processing device having electrically erasable programmable

A semiconductor integrated circuit having a complementary MOS structure, comprises an output buffer control portion of a complementary MOS inverter structure for inputting a logical output of an internal logic circuit, an output buffering MOS transistor of a first conductive type for receiving output of the output buffer control portion as a gate input and externally outputting a logical output, and level shifting means for causing level shift of a source potential of a second conductive type MOS transistor to be lower than a power source potential in a magnitude corresponding to a threshold value of the second conductive type MOS transistor.

CMOS output circuit with open drain transistor

A microcomputer having an electrically erasable and programmable nonvolatile memory into which data is written without prolonging the data write processing time, even when a data read request is issued during the data write processing operation. The microcomputer includes a data erasing/writing/reading control circuit which coordinates the writing and reading of data to and from memory. The control circuit includes a timer for counting a predetermined number of counts during the data write process corresponding to the time period required to positively write data into the memory. If a data read request occurs during the data write process, the counting of the timer is suspended while the data is read out from the memory. After the data read process is completed, the data write process is resumed, and the timer continues counting toward the predetermined count from the count at which it was suspended. When the timer reaches the predetermined count, the data has been positively written into memory, and the data write process is terminated.

Electrically erasable and programmable non-volatile memory (EEPROM),

An EEPROM device comprises a memory cell array having a plurality of non-volatile memory cells respectively disposed at locations defined by word lines and bit lines and memorizing pieces of data information in a rewriteable manner, respectively, a row address decoder circuit responsive to an address signal indicative of a row address for selectively activating one of the word lines, a column address decoder circuit responsive to an address signal indicative of a column address for selecting one of the bit lines, and a data control unit selectively carrying out erasing, write-in and read-out operations on one of the non-volatile memory cells, in which the row address decoder circuit is further operative to concurrently activate every second word line in the presence of the row address signal indicative of a first state and to concurrently activate the other word lines in the presence of the row address signal indicative of a second state in a testing mode of operation, and in which the data control unit carries out the erase and write-in operations on a plurality of the non-volatile memory cells coupled to the word lines to be activated in the testing mode of operation.

Non-volatile semiconductor memory device having an improved testing mode

A single data signal is transmitted by two transmitters to two radio zones having an overlapping zone therebetween. The data signal is frequency or phase modulated and is mixed in the transmitters with RF carrier waves of equal frequency. The data signal to one of the transmitters is delayed between 5.degree. and 50.degree. with respect to the original data signal to provide a phase difference between the transmitted signals.

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Tokyo, Japan

Toshihide Tsuboi