Renesas Electronics Corporation

Globalfoundries Inc.

International Business Machines Corporation

Toshiharu Nagumo

Kangguo Cheng

Bruce Bennett Doris

Ali Khakifirooz

Ajey Poovannummoottil Jacob

Steven J Bentley

Murat Kerem Akarvardar

Jody Alan Fronheiser

Kiyoshi Takeuchi

Takashi Hase

Ippei Kume

Tomohiro Hirai

Shogo Mochizuki

Hiroshi Takeda

Toyoji Yamamoto

A semiconductor device and method making it utilize a three-dimensional channel region comprising a core of a first semiconductor material and an epitaxial covering of a second semiconductor material. The first and second semiconductor materials have respectively different lattice constants, thereby to create a strain in the epitaxial covering. The devices are formed by a gate-last process, so that the second semiconductor material is deposited only after the high temperature processes have been performed. Consequently, the lattice strain is not substantially relaxed, and the improved performance benefits of the lattice strained channel region are not compromised.

Semiconductor device having compressively strained channel region and method of making same

Performance of a semiconductor device is improved. The semiconductor device includes a substrate composed of silicon, a semiconductor layer composed of p-type nitride semiconductor provided on the substrate, and a transistor including a channel layer provided on the semiconductor layer. The semiconductor device further includes an n-type source region provided in the channel layer, and an n-type drain region provided in the channel layer separately from the source region in a plan view. Each of the source region and the drain region is in contact with the semiconductor layer.

High-electron-mobility transistor with protective diode

A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Self-aligned dual-height isolation for bulk FinFET

Disclosed is a semiconductor device that reduces the area of a transistor in a ReRAM. A plurality of memory cells differ from each other in the combination of bit line and plate line. The potential of plate line PLis a forming voltage. By contrast, the potentials of the other plate lines are +Vi. The potential of bit line BLis 0 V (ground potential). By contrast, the potentials of the other bit lines are +Vi. The potential of is +Vgf. By contrast, the potentials of the other word lines are +Vi.

Semiconductor device and forming method

A semiconductor device and method making it comprises pFETs with an SiGe channel and nFETs with an Si channel, formed on an SOI substrate. Improved uniformity of fin height and width is attained by forming the fins additively by depositing an SiGe layer on the SOI substrate and forming first fins from the superposed SiGe layer and underlying thin Si film of the SOI substrate. Second fins of Si can then be formed by replacing the upper SiGe portions of selected first fins with Si.

Semiconductor device having finFET structures and method of making same

Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

Device isolation in FinFET CMOS

To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1&#xd7;10/cm, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.

Semiconductor device with group-III nitride compound semiconductor layer on substrate for transistor

A semiconductor device includes a channel structure formed on a substrate, the channel structure being formed of a semiconductor material. A gate structure covers at least a portion of the surface of the channel structure and is formed of a film of insulation material and a gate electrode. A source structure is connected to one end of the channel structure, and a drain structure is connected to the other end of the channel structure. The channel structure has a non-uniform composition, in a cross-sectional view, that provides a reduction of a leakage current of the semiconductor device relative to a leakage current that would result from a uniform composition.

Field effect transistor with channel core modified to reduce leakage current and method of fabrication

A semiconductor device includes a substrate and a source structure and a drain structure formed on the substrate. At least one nanowire structure interconnects the source structure and drain structure and serves as a channel therebetween. A gate structure is formed over said at least one nanowire structure to provide a control of a conductivity of carriers in the channel, and the nanowire structure includes a center core serving as a backbias electrode for the channel.

Field effect transistor with channel core modified for a backgate bias and method of fabrication

Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.

Growing community of inventors

Kanagawa, Japan

Toshiharu Nagumo