International Business Machines Corporation

Globalfoundries Inc.

Semivation, LLC

International Business Machines Corporataion

International Business Machines Coirporation

Toshiharu Furukawa

David V Horak

Mark Charles Hakey

Steven J Holmes

Charles W Koburger, Iii

Jack Allan Mandelman

William R Tonti

Peter H Mitchell

Paul A Rabidoux

Larry Alan Nesbit

William H Ma

Anthony I Chou

Kangguo Cheng

Robert Russell Robison

James Albert Slinkman

Richard Quimby Williams

Mark Eliot Masters

Carl John Radens

Veeraraghavan S Basker

Ethan Harrison Cannon

William H-l Ma

Jeffrey W Sleight

Robert J Gauthier, Jr

Gary Bela Bronner

Byeongju Park

Thomas Safron Kanarsky

Bruce Bennett Doris

Chung H Lam

John J Ellis-Monaghan

Wilfried Haensch

Howard L Kalter

Zhibin Ren

John Gerard Gaudiello

Jeffrey John Welser

Dinkar Virendra Singh

Xuefeng Hua

Oleg Gluschenkov

Wesley Charles Natzle

Johnathan E Faltermeier

Naim Moumen

Ashima B Chakravarti

William Hsioh-Lien Ma

Jason E Cummings

Edward J Nowak

Dureseti Chidambarrao

Jed Hickory Rankin

Son Van Nguyen

Michael Patrick Chudzik

Edmund Juris Sprogis

Renee Tong Mo

Wagdi William Abadeer

Kiran V Chatty

James Spiros Nakos

Ulrike Gruening

Charles Thomas Black

Stanislav Polonsky

Leathen Shi

James Marc Leas

Douglas C La Tulipe, Jr

David James Frank

Kathryn Wilder Guarini

Jerzy Maria Zalesinski

Diane Catherine Boyd

Dan Moy

Shunhua Thomas Chang

Delbert Raymond Cecchi

Thomas S Rupp

Paul Daniel Kirsch

Jeffrey P Gambino

Claude Louis Bertin

Steven H Voldman

Steven M Shank

Arne Watson Ballantine

Hariklia Deligianni

Kirk David Peterson

Chengwen Pei

John Michael Cotte

Dirk Pfeiffer

Vamsi Krishna Paruchuri

Jin Cai

Qiqing Christine Ouyang

Rajarao Jammy

William F Clark, Jr

Roger Allen Booth, Jr

Edward William Kiewra

Erik L Hedberg

Joseph Francis Shepard, Jr

H Bernhard Pogge

Rosemary A Previti-Kelly

William P Parker

Arpan Pravin Mahorowala

Patrick Ronald Varekamp

Daniel A Corliss

Mary Elizabeth Weybright

Jay Sanford Burnham

Sadanand Vinayak Deshpande

Katsunori Onishi

Qingyun Yang

Len Yuan Tsou

Glenn Robert Miller

A method of cleaving off a daughter single crystal substrate from a parent single crystal substrate includes providing a stress-mandrel and the parent a single crystal substrate. The parent single crystal substrate has a major surface and an edge surface that intersects the major surface. The major surface extends along a major surface plane. The stress-mandrel has a stress-mandrel coefficient of thermal expansion that is higher than the parent single crystal coefficient of thermal expansion. The method includes bonding the stress-mandrel to the major surface, and cooling the parent single crystal substrate and the stress-mandrel. The cooling of the parent single crystal substrate bonded to the stress-mandrel provides a thermal stress in the parent single crystal substrate sufficient to cleave the parent single crystal substrate. The cleaving extends substantially along a plane parallel to the plane of the major surface. In one embodiment the cleaved daughter substrate was used to make a photovoltaic cell.

Method of cleaving a single crystal substrate parallel to its active planar surface and method of using the cleaved daughter substrate

Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess.

Extremely thin semiconductor-on-insulator (ETSOI) layer

Disclosed is a semiconductor-on-insulator (SOI) structure (e.g., an SOI field effect transistor (FET)) and method of forming the SOI structure so as to have sub-insulator layer void(s) selectively placed so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device and the second section may contain a second device. Alternatively, the first and second sections may comprise different regions of the same device. For example, in an SOI FET, sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate.

Semiconductor-on-insulator (SOI) structure with selectivity placed sub-insulator layer void(s) and method of forming the SOI structure

An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.

Creating extremely thin semiconductor-on-insulator (ETSOI) having substantially uniform thickness

A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.

Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness

Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.

Carbon nanotube structures for enhancement of thermal dissipation from semiconductor modules

A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.

Selective deposition of germanium spacers on nitride

A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

Microelectronic structure by selective deposition

Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.

Anti-fuse device structure and electroplating circuit structure and method

Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.

Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure

A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial material that is deposited over a structure layer and covered by a cover layer. The sacrificial material layer and the cover layer are patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the material layer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.

CMOS gate structures fabricated by selective oxidation

A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)

A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.

Field effect transistor

Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.

Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (SOI) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor

A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby

Growing community of inventors

Essex Junction, VT, United States of America

Toshiharu Furukawa